EP2S60F1020I4 Altera, EP2S60F1020I4 Datasheet - Page 222

• Manufacturer Part Number: EP2S60F1020I4
• Description: IC STRATIX II FPGA 60K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F1020I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 718
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 718
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1903; EP2S60F1020I4

Duty Cycle Distortion
5–86
Stratix II Device Handbook, Volume 1
Note to
(1)
Notes to
(1)
(2)
LVDS/ HyperTransport
technology
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path
Row DDIO Output I/O
The DCD specification is based on a no logic array noise condition.
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
Table
Standard
Standard
Table
5–86:
5–87:
Note (1)
Maximum DCD (PLL Output Clock Feeding
Maximum DCD (PLL Output Clock Feeding
Note (1)
-3 Device
-3 Device
145
100
140
155
180
180
85
85
65
60
50
70
60
60
55
85
DDIO Clock Port)
DDIO Clock Port)
-4 & -5 Device
-4 & -5 Device
160
110
100
155
100
180
95
75
70
65
80
70
70
70
180
Altera Corporation
-
April 2011
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