EP1SGX25DF1020C5 Altera, EP1SGX25DF1020C5 Datasheet - Page 43

• Manufacturer Part Number: EP1SGX25DF1020C5
• Description: IC STRATIX GX FPGA 25K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF1020C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 607
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 607
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
The receiver PLL can also drive the fast regional, regional clocks, and
local routing adjacent to the associated transceiver block.
through
used by the recovered clock.
In the EP1SGX25 device, the receiver PLL recovered clocks from
transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2
and 3 drive RCLK[7..6]. The regional clocks feed logic in their
associated regions.
Figure 2–28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock
Connection
In addition, the receiver PLL’s recovered clocks can drive fast regional
lines (FCLK) as shown
in their associated regions.
2–31
show which fast regional and regional clock resource can be
Figure
2–29. The fast regional clocks can feed logic
PLD
Stratix GX Device Handbook, Volume 1
RCLK[11..10]
RCLK[9..8]
Transceiver Blocks
Stratix GX Transceivers
Stratix GX
Block 0
Block 1
Block 2
Block 3
Figures 2–28
2–33