EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 122

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EP1SGX40DF1020C6N

Manufacturer Part Number
EP1SGX40DF1020C6N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40DF1020C6N

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX40DF1020C6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX40DF1020C6N
Manufacturer:
ALTERA
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Part Number:
EP1SGX40DF1020C6N
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Digital Signal Processing Block
4–56
Stratix GX Device Handbook, Volume 1
Pipeline/Post Multiply Register
The output of 9
to pipeline multiply-accumulate and multiply-add/subtract functions.
For 36
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator, a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplier. You can configure the adder/output block to use output
registers in any mode, and must use output registers for the accumulator.
The system cannot use adder/output blocks independently of the
multiplier.
×
36-bit multipliers, this register pipelines the multiplier function.
Figure 4–33
×
9- or 18
shows the adder and output stages.
×
18-bit multipliers can optionally feed a register
Altera Corporation
February 2005

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