EP1SGX40DF1020C6 Altera, EP1SGX40DF1020C6 Datasheet - Page 29
EP1SGX40DF1020C6
Manufacturer Part Number
EP1SGX40DF1020C6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Altera Corporation
June 2006
Figure 2–15. Word Aligner in Bit-Slip Mode
In the bit-slip mode, the byte boundary can be modified by a barrel shifter
to slip the byte boundary one bit at a time via a user-controlled bit-slip
port. The bit-slip mode supports both 8-bit and 10-bit data paths
operating in a single or double-width mode.
The pattern detector is active in the bit-slip mode, and it detects the
user-defined pattern that is specified in the MegaWizard
Manager.
The bit-slip mode is available only in Custom mode and SONET mode.
Figure 2–16
10-Bit
Mode
shows the word aligner in 16-bit mode.
Mode
A1A2
Patterm Detector
16-Bit
Mode
A1A1A2A2
Mode
Mode
7-Bit
Stratix GX Device Handbook, Volume 1
Bit-Slip
Mode
Word Aligner
Stratix GX Transceivers
Alignment
Manual
Mode
®
Plug-In
2–19
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