EP1SGX40DF1020C6 Altera, EP1SGX40DF1020C6 Datasheet - Page 36
EP1SGX40DF1020C6
Manufacturer Part Number
EP1SGX40DF1020C6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Figure 2–21. Data Path in Serial Loopback Mode
2–26
Stratix GX Device Handbook, Volume 1
Deserializer
Active Path
Non-Active Path
Recovery
Clock
Unit
Serializer
Aligner
Word
Loopback Modes
The Stratix GX transceiver has built-in loopback modes to aid in debug
and testing. The loopback modes are set in the Stratix GX MegaWizard
Plug-In Manager in the Quartus II software. Only one loopback mode can
be set at any single instance of the transceiver block. The loopback mode
applies to all used channels in a transceiver block.
The available loopback modes are:
■
■
■
Serial Loopback
Serial loopback exercises all the transceiver logic except for the output
buffer and input buffer. The loopback function is dynamically switchable
through the rx_slpbk port on a channel by channel basis. The V
output reduced. If you select 400 mV, the output is tri-stated when the
serial loopback option is selected.
serial loopback mode.
Channel
Aligner
BIST PRBS
Verifier
Serial loopback
Parallel loopback
Reverse serial loopback
BIST PRBS
Generator
Encoder
8B/10B
Matcher
Rate
Serializer
Byte
Decoder
8B/10B
Figure 2–21
Compensation
Phase
FIFO
Deserializer
Byte
shows the data path in
Altera Corporation
Incremental
Verifier
Compensation
BIST
Phase
FIFO
June 2006
OD
Generator
BIST
of the