EP1SGX40GF1020C5 Altera, EP1SGX40GF1020C5 Datasheet - Page 59

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EP1SGX40GF1020C5

Manufacturer Part Number
EP1SGX40GF1020C5
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40GF1020C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Altera Corporation
August 2005
Figure 3–7. PLL & Channel Layout in EP1SGX40 Devices
Notes to
(1)
(2)
(3)
Corner PLLs do not support DPA.
Not all eight phases are used by the receiver channel or transmitter channel in
non-DPA mode.
The center PLLs can only clock 20 transceivers in either direction. Using Fast PLL2,
you can clock a total of 40 transceivers, 20 in each direction.
Figure
22 Rows
23 Rows
3–7:
1 Transmitter
1 Transmitter
1 Transmitter
1 Transmitter
1 Receiver
1 Receiver
1 Receiver
1 Receiver
INCLK0
INCLK1
CLKIN
CLKIN
Source-Synchronous Signaling With DPA
Stratix GX Device Handbook, Volume 1
PLL (1)
PLL (1)
PLL 1
PLL 2
Fast
Fast
8
8
Eight-Phase
Clock
Eight-Phase
Clock
Notes
(1), (2),
3–9
(3)

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