EP2SGX90EF1152C3ES Altera, EP2SGX90EF1152C3ES Datasheet - Page 47
![IC STRATIX II GX 90K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX90EF1152C3ES
Manufacturer Part Number
EP2SGX90EF1152C3ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C3ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1763
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Altera Corporation
October 2007
REFCLK[1..0]
Transmitter PLL
Receiver PLL
Global clock
(driven from an
input pin)
Inter-transceiver
lines
Table 2–11. Available Clocking Connections for Transceivers
Source
Transmitter
PLL
v
v
v
Table 2–11
transceivers.
Clock Resource for PLD-Transceiver Interface
For the regional or global clock network to route into the transceiver, a
local route input output (LRIO) channel is required. Each LRIO clock
region has up to eight clock paths and each transceiver block has a
maximum of eight clock paths for connecting with LRIO clocks. These
resources are limited and determine the number of clocks that can be used
between the PLD and transceiver blocks.
LRIO resources available for Stratix II GX devices with different numbers
of transceiver blocks.
Tables 2–12
to the transceiver block.
Region0
8 LRIO clock
Region1
8 LRIO clock
Table 2–12. Available Clocking Connections for Transceivers in 2SGX30D
Region
Receiver PLL
summarizes the possible clocking connections for the
through
v
v
v
Global
Clock
2–15
v
v
Clock Resource
Global Clock
show the connection of the LRIO clock resource
Destination
RCLK 20-27
RCLK 12-19
v
v
v
Regional
Clock
Stratix II GX Device Handbook, Volume 1
Table 2–12
Regional
8 Clock I/O
Clock
Bank 13
v
v
v
v
Stratix II GX Architecture
Transceiver
shows the number of
Inter-Transceiver
8 Clock I/O
Bank 14
v
Lines
v
2–39
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