EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 272
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SE230F29C3N PDF datasheet #6
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Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL, while the alignment clock comes from the write-leveling delay chains.
(4) These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.
Figure
Half-Rate Clock (3)
7–32:
From Core (2)
From Core (2)
(wdata2) (2)
(wdata0) (2)
(wdata3) (2)
(wdata1) (2)
From Core
From Core
From Core
From Core
Half Data Rate to Single Data Rate Output-Enable Registers
D
D
D
D
D
D
DFF
DFF
Half Data Rate to Single Data Rate Output Registers
DFF
DFF
DFF
DFF
Q
Q
Q
Q
Q
Q
Alignment
Clock (3)
D
D
D
DFF
DFF
DFF
Q
Q
Q
0
1
0
1
0
1
D
D
D
DFF
DFF
DFF
(Note 1)
Q
Q
Q
D
D
D
DFF
DFF
DFF
Q
Q
Q
Alignment Registers (4)
Alignment Registers (4)
D
D
D
DFF
DFF
DFF
Q
Q
Q
Clock (5)
Write
DFF
DFF
Output Reg Bo
Double Data Rate Output-Enable Registers
OE Reg B
Output Reg Ao
DFF
OE Reg A
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
1
0
OR2
TRI
DQ or DQS
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