EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 323
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (11Mb)
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
February 2011 Altera Corporation
Using Both Center Left and Right PLLs
You can use both center left and right PLLs simultaneously to drive DPA-disabled
channels on upper and lower differential banks. Unlike DPA-enabled channels, the
center left and right PLLs can drive cross-banks. For example, the upper-center left
and right PLL can drive the lower differential bank at the same time the lower center
left and right PLL is driving the upper differential bank, and vice versa, as shown in
Figure
Figure 8–36. Both Center Left and Right PLLs Driving Cross-Bank DPA-Disabled Channels
Simultaneously
8–36.
Left/Right PLL
Left/Right PLL
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
Reference
Reference
Center
Center
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
CLK
CLK
Stratix IV Device Handbook Volume 1
8–45
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