XCS40XL-4PQ240C Xilinx Inc, XCS40XL-4PQ240C Datasheet - Page 56

no-image

XCS40XL-4PQ240C

Manufacturer Part Number
XCS40XL-4PQ240C
Description
IC 3.3V FPGA COMM. TEMP 240PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet

Specifications of XCS40XL-4PQ240C

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
192
Number Of Gates
40000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Case
QFP240
Dc
03+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1039179A
Q1150517
XCS40XL4PQ240C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
Quantity:
129
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
Quantity:
490
Part Number:
XCS40XL-4PQ240C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
0
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
Quantity:
1
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
56
Notes:
1.
Write Operation
Read Operation
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
WCTS
WPTS
WSTS
WOTS
ASTS
DSTS
WOS
IHCK
WCS
WPS
WSS
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
ASS
DSS
RCT
IHO
ILO
ICK
RC
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
Address read cycle time
Data Valid after address change (no Write
Enable)
Address setup time before clock K
Single Port RAM
www.xilinx.com
Size
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
16x2
32x1
16x2
32x1
16x2
32x1
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
(1)
Min
7.7
7.7
3.1
3.1
1.3
1.5
1.5
1.8
1.4
1.3
0.0
2.6
3.8
0.6
1.3
-
-
-
-
-5
Max
4.5
5.4
1.0
1.7
Speed Grade
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
8.4
8.4
3.6
3.6
1.5
1.7
1.7
2.1
1.6
1.5
0.0
3.1
5.5
0.7
1.6
-
-
-
-
DS060 (v1.8) June 26, 2008
-4
Product Specification
Max
5.3
6.3
1.1
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R

Related parts for XCS40XL-4PQ240C