XCS40XL-4PQ240C Xilinx Inc, XCS40XL-4PQ240C Datasheet - Page 83
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XCS40XL-4PQ240C
Manufacturer Part Number
XCS40XL-4PQ240C
Description
IC 3.3V FPGA COMM. TEMP 240PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS40XL-4PQ240C
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
192
Number Of Gates
40000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Case
QFP240
Dc
03+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1039179A
Q1150517
XCS40XL4PQ240C
Q1150517
XCS40XL4PQ240C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
Quantity:
129
Company:
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX
Quantity:
490
Part Number:
XCS40XL-4PQ240C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Revision History
The following table shows the revision history for this document.
DS060 (v1.8) June 26, 2008
Product Specification
11/20/98
01/06/99
03/02/00
09/19/01
06/27/02
06/26/08
Date
R
Version
1.3
1.4
1.5
1.6
1.7
1.8
Added Spartan-XL specs and Power Down.
All Spartan-XL -4 specs designated Preliminary with no changes.
Added CS package, updated Spartan-XL specs to Final.
Reformatted, updated power specs, clarified configuration information. Removed T
soldering information from Absolute Maximum Ratings table. Changed
Serial Mode Characteristics: T
Configuration Switching Characteristics: T
RAM Bits to
Clarified Express Mode pseudo daisy chain. Added new Industrial options. Clarified
XCS30XL CS280 V
Noted that PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for
XCS30 only, are discontinued by
maximum delay of reconfiguration in
page
Specifications, page
35. Added reference to Pb-free package options and provided link to
Table
1; added
www.xilinx.com
CC
81. Updated links.
pinout.
Start-Up, page 36
CCH
PDN2004-01
Spartan and Spartan-XL FPGA Families Data Sheet
, T
CCL
Delaying Configuration After Power-Up,
Description
from 45 to 40 ns. Changed Master Mode
CCLK
. Extended description of recommended
min. from 80 to 100 ns. Added Total Dist.
characteristics.
Figure
Package
26: Slave
SOL
83