XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 188

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
Module 4 of 4
102
Notes:
1.
2.
3.
4.
5.
Pair
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
AO in the XCV1000E, 2000E.
AO in the XCV1000E, 1600E.
AO in the XCV2000E.
AO in the XCV1600E.
AO in the XCV1000E.
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
M39
M38
M42
R38
P39
P38
N39
N41
K38
H39
H38
G40
G39
G42
E42
E41
D41
T38
T42
L39
L40
L41
F40
F41
Pin
J40
P
R39
R42
R40
R41
N42
M40
M41
H42
G38
G41
T41
P42
P40
P41
K40
K42
K41
F42
F39
E40
E39
L38
J39
J38
J41
Pin
N
AO
√
1
2
4
2
1
3
√
√
2
√
√
2
5
√
√
1
2
√
1
2
4
2
1
3
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
FG900 Fine-Pitch Ball Grid Array Package
XCV600E, XCV1000E, and XCV1600E devices in the
FG900 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V
eral I/O. Immediately following
Differential Pair information.
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_VREF_L5N_YY
IO_VREF_L2N_Y
Pin Description
IO_L0N_YY
IO_L0P_YY
IO_L4N_YY
IO_L4P_YY
IO_L5P_YY
IO_L1N_Y
IO_L3N_Y
IO_L1P_Y
IO_L2P_Y
IO_L3P_Y
GCK3
Production Product Specification
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DS022-4 (v2.5) March 14, 2003
REF
Table
, it can be used as gen-
26, see
Table 27
Pin #
A13
C14
D13
E14
K11
F14
L13
J10
C15
D10
G15
C5
C6
D8
K12
C4
A7
E9
F9
F7
A3
B4
G8
E6
D5
H9
A4
D6
E7
B5
4
5
4
3
1
4
4
4
5
4
4
4
4
4
4
5
5
5
for
R