XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 20

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
.
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
Module 2 of 4
14
Resistor on Done
Optional Pull-up
(Output)
DOUT
CCLK
Figure 14: Slave-Serial Mode Programming Switching Characteristics
DIN
PROGRAM
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor
1
Figure 13: Master/Slave Serial Mode Circuit Diagram
of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω
pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,
DriveDONE should be selected only for the last device in the configuration chain.
1 T
M2
PROGRAM
DONE
M0 M1
VIRTEX-E
DCC
MASTER
SERIAL
DOUT
CCLK
DIN
INIT
2 T
3 T
CCD
CCO
www.xilinx.com
1-800-255-7778
4 T
3.3V
CCH
330 Ω
(Low Reset Option Used)
CLK
DATA
CE
RESET/OE
In a full master/slave system
device operates in master-serial mode. The remaining
devices operate in slave-serial mode. The SPROM RESET
pin is driven by INIT, and the CE input is driven by DONE.
There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in
XC1701L
CEO
Figure 15: Serial Configuration Flowchart
FPGA checks data using CRC
FPGA enters start-up phase
and pulls INIT Low on error.
clearing pass and releases
causing DONE to go High.
If no CRC errors found,
configuration memory.
N/C
FPGA starts to clear
FPGA makes a final
Once per bitstream,
INIT when finished.
5 T
DIN
CCLK
PROGRAM
DONE
M2
CCL
M0 M1
N/C
XC4000XL,
VIRTEX-E,
SLAVE
DOUT
INIT
Production Product Specification
Configuration Completed
Load a Configuration Bit
XCVE_ds_013_050103
Set PROGRAM = High
DS022-2 (v2.6.1) June 15, 2004
Apply Power
Release INIT
Bitstream?
X5379_a
(Figure
End of
INIT?
Figure
High
Yes
Low
No
13), the left-most
15.
If used to delay
configuration
ds009_15_111799
R