XC2V250-5CSG144I Xilinx Inc, XC2V250-5CSG144I Datasheet - Page 2

• Manufacturer Part Number: XC2V250-5CSG144I
• Description: IC FPGA VIRTEX-II 250K 144-CSBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V250-5CSG144I

• Number Of Labs/clbs: 384
• Total Ram Bits: 442368
• Number Of I /o: 92
• Number Of Gates: 250000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

DS031-1 (v3.5) November 5, 2007
Summary of Virtex-II™ Features
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© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031-1 (v3.5) November 5, 2007
Product Specification
Industry First Platform FPGA Solution
IP-Immersion Architecture
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SelectRAM™ Memory Hierarchy
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High-Performance Interfaces to External Memory
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Arithmetic Functions
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Flexible Logic Resources
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High-Performance Clock Management Circuitry
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Active Interconnect Technology
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SelectIO™-Ultra Technology
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Densities from 40K to 8M system gates
420 MHz internal clock speed (Advance Data)
840+ Mb/s I/O (Advance Data)
3 Mb of dual-port RAM in 18 Kbit block SelectRAM
resources
Up to 1.5 Mb of distributed SelectRAM resources
DRAM interfaces
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SRAM interfaces
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CAM interfaces
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 93,184 internal registers / latches with Clock
Enable
Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products
support
Internal 3-state bussing
Up to 12 DCM (Digital Clock Manager) modules
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16 global clock multiplexer buffers
Fourth generation segmented routing structure
Predictable, fast routing delay, independent of
fanout
Up to 1,108 user I/Os
19 single-ended and six differential standards
Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
SDR / DDR SDRAM
Network FCRAM
Reduced Latency DRAM
SDR / DDR SRAM
QDR™ SRAM
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
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www.xilinx.com
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Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
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SRAM-Based In-System Configuration
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0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
1.5V (V
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IEEE 1149.1 Compatible Boundary-Scan Logic
Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Three Standard Fine Pitches (0.80 mm,
1.00 mm, and 1.27 mm)
Wire-Bond BGA Devices Available in Pb-Free
Packaging (
100% Factory Tested
CCAUX
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
Differential Signaling
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Proprietary high-performance SelectLink
Technology
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Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
Fast SelectMAP configuration
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
CCINT
Introduction and Overview
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR input and output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
Auxiliary and V
Virtex-II Platform FPGAs:
www.xilinx.com/pbfree)
) Core Power Supply, Dedicated 3.3V
CCO
I/O Power Supplies
Product Specification
Module 1 of 4
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