XC2V250-5CSG144I Xilinx Inc, XC2V250-5CSG144I Datasheet - Page 87

• Manufacturer Part Number: XC2V250-5CSG144I
• Description: IC FPGA VIRTEX-II 250K 144-CSBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V250-5CSG144I

• Number Of Labs/clbs: 384
• Total Ram Bits: 442368
• Number Of I /o: 92
• Number Of Gates: 250000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II source-synchronous
transmitter and receiver data-valid windows.
Table 45: Duty Cycle Distortion and Clock-Tree Skew
Table 46: Package Skew
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the
Duty Cycle Distortion
Clock Tree Skew
Package Skew
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T
T
in the I/O.
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
to Ball (7.1ps per mm).
package.
DCD_CLK0
DCD_CLK180
Description
R
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
(1)
Description
(2)
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
(1)
T
T
DCD_CLK180
Symbol
T
DCD_CLK0
CKSKEW
T
Symbol
PKGSKEW
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Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
All
All
XC2V3000 / FF1152
XC2V4000 / FF1152
XC2V4000 / FF1517
XC2V6000 / FF1152
XC2V6000 / FF1517
XC2V1000 / FF896
XC2V3000 / BF957
XC2V4000 / BF957
XC2V6000 / BF957
Device/Package
140
100
100
400
500
50
50
50
50
50
80
80
-6
Speed Grade
140
100
100
400
500
600
50
50
50
50
50
80
80
-5
Value
140
110
110
450
550
650
130
115
130
130
200
140
105
105
50
60
60
60
60
90
90
90
-4
Module 3 of 4
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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ps
ps
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