XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 141
XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Additional Block RAM Primitives
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
In addition to RAMB16, some added block RAM primitives are available for Virtex-4
FPGA designers allowing the implementation of various block RAM sizes with preset
configurations.
The input and output data buses are represented by two buses for 9-bit width (8+1), 18-bit
width (16+2), and 36-bit width (32+4) configurations. The ninth bit associated with each
byte can store parity or error correction bits. No specific function is performed on this bit.
The separate bus for parity bits facilitates some designs. However, other designs safely use
a 9-bit, 18-bit, or 36-bit bus by merging the regular data bus with the parity bus.
Read/write and storage operations are identical for all bits, including the parity bits.
Some block RAM attributes can only be configured using the RAMB16 primitive (e.g.,
pipeline register, cascade, etc.). See the
Figure 4-10
DOPA, and the corresponding signals on port B are buses.
Table 4-6
lists the available dual-port primitives for synthesis and simulation.
shows the generic dual-port block RAM primitive. DIA, DIPA, ADDRA, DOA,
Figure 4-10: Dual-Port Block RAM Primitive
www.xilinx.com
DIA[X:0]
DIPA[X:0]
ADDRA[X:0]
WEA
ENA
SSRA
DIB[Y:0]
DIPB[Y:0]
ADDRB[Y:0]
WEB
ENB
SSRB
CLKA
CLKB
RAMB16_SX_SY
“Block RAM Attributes”
DOPA[#:0]
DOPB[#:0]
DOA[#:0]
DOB[#:0]
Additional Block RAM Primitives
ug070_4_10_071204
section.
141
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