XC5VLX30-1FFG324I Xilinx Inc, XC5VLX30-1FFG324I Datasheet - Page 202
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XC5VLX30-1FFG324I
Manufacturer Part Number
XC5VLX30-1FFG324I
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG324I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-7: General Slice Timing Parameters
202
Combinatorial Delays
Sequential Delays
Setup and Hold Times for Slice Sequential Elements
Set/Reset
Notes:
1. This parameter includes a LUT configured as two five-input functions.
2. T
T
T
T
T
T
T
T
T
T
T
F
TOG
ILO
ILO_2
ILO_3
CKO
CKLO
DICK
CECK
SRCK
RPW
RQ
XXCK
(1)
/T
/T
/T
= Setup Time (before clock edge), and T
CKDI
CKSR
CKCE
Parameter
Timing Parameters
Table 5-7
Figure
5-25.
shows the general slice timing parameters for a majority of the paths in
A/B/C/D inputs to A/B/C/D
outputs
A/B/C/D inputs to
AMUX/CMUX outputs
A/B/C/D inputs to BMUX
output
FF Clock (CLK) to
AQ/BQ/CQ/DQ outputs
Latch Clock (CLK) to
AQ/BQ/CQ/DQ outputs
AX/BX/CX/DX inputs
CE input
SR/BY input
CKXX
Function
= Hold Time (after clock edge).
www.xilinx.com
(2)
Propagation delay from the A/B/C/D inputs of
the slice, through the look-up tables (LUTs), to the
A/B/C/D outputs of the slice (six-input
function).
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs and
F7AMUX/F7BMUX to the AMUX/CMUX
outputs (seven-input function).
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs, F7AMUX/F7BMUX,
and F8MUX to the BMUX output (eight-input
function).
Time after the clock that data is stable at the
AQ/BQ/CQ/DQ outputs of the slice sequential
elements (configured as a flip-flop).
Time after the clock that data is stable at the
XQ/YQ outputs of the slice sequential elements
(configured as a latch).
Time before/after the CLK that data from the
AX/BX/CX/DX inputs of the slice must be stable
at the D input of the slice sequential elements
(configured as a flip-flop).
Time before/after the CLK that the CE input of
the slice must be stable at the CE input of the slice
sequential elements (configured as a flip-flop).
Time before/after the CLK that the SR (Set/Reset)
and the BY (Rev) inputs of the slice must be stable
at the SR/Rev inputs of the slice sequential
elements (configured as a flip-flop).
Minimum Pulse Width for the SR (Set/Reset) and
BY (Rev) pins.
Propagation delay for an asynchronous Set/Reset
of the slice sequential elements. From the SR/BY
inputs to the AQ/BQ/CQ/DQ outputs.
Toggle Frequency – Maximum frequency that a
CLB flip-flop can be clocked: 1 / (T
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CH
+ T
CL
).
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