XC5VLX30-1FFG324I Xilinx Inc, XC5VLX30-1FFG324I Datasheet - Page 268
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-1FFG324I
Manufacturer Part Number
XC5VLX30-1FFG324I
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG324I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
XC5VLX30-1FFG324I
Manufacturer:
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Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-59
X-Ref Target - Figure 6-60
268
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI_18
External Termination
DIFF_HSTL_II_18
DIFF_HSTL_II_18
DIFF_HSTL_II_18
DCI
Figure 6-59: Differential HSTL (1.8V) Class II DCI Unidirectional Termination
+
–
Figure 6-60: Differential HSTL (1.8V) Class II Bidirectional Termination
V
V
CCO
CCO
Figure 6-59
differential HSTL Class II (1.8V) with unidirectional DCI termination.
Figure 6-60
differential HSTL Class II (1.8V) with bidirectional termination.
= 1.8V
= 1.8V
2R
2R
2R
2R
IOB
IOB
VRP
VRN
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
shows a sample circuit illustrating a valid termination technique for
shows a sample circuit illustrating a valid termination technique for
V
V
TT
TT
= 0.9V
= 0.9V
50Ω
50Ω
www.xilinx.com
Z 0
Z 0
Z 0
Z 0
IOB
V
V
CCO
CCO
V
V
TT
50Ω
TT
50Ω
2R
2R
2R
2R
= 1.8V
= 1.8V
= 0.9V
= 0.9V
VRP
VRN
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
IOB
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_18
DIFF_HSTL_II_18
DIFF_HSTL_II_18
ug190_6_57_030306
+
–
+
–
ug190_6_56_121506
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