XC6VCX75T-2FFG784C Xilinx Inc, XC6VCX75T-2FFG784C Datasheet - Page 29

• Manufacturer Part Number: XC6VCX75T-2FFG784C
• Description: IC FPGA VIRTEX 6 74K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-2FFG784C

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 38: IOB Switching Characteristics (Cont’d)
Table 39: IOB 3-state ON Output Switching Characteristics (T
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 40
Table 40: Input Delay Measurement Methodology
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
DIFF_SSTL18_II_T_DCI
DIFF_SSTL15
DIFF_SSTL15_DCI
DIFF_SSTL15_T_DCI
T
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL, Class III
HSTL, Class I & II, 1.8V
HSTL, Class III 1.8V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
HT (HyperTransport), 2.5V
IOTPHZ
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
values listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the V
The value given is the differential output voltage.
shows the test setup parameters used for measuring input delay.
Symbol
I/O Standard
Description
T input to Pad high-impedance
L
and V
H
.
1.09
1.06
1.06
1.06
-2
Speed Grade
Description
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I, HSTL_II
HSTL_III
HSTL_I_18, HSTL_II_18
HSTL_III_18
SSTL3_I, SSTL3_II
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
LVDS_25
LVDSEXT_25
LDT_25
I /O Standard Attribute
T
IOPI
www.xilinx.com
REF
1.09
1.06
1.06
1.06
REF
-1
values. Reported delays reflect worst case of these measurements. V
/ V
MEAS
IOTPHZ
1.67
1.71
1.68
1.68
parameters found in IBIS models and/or noted in
-2
Speed Grade
)
T
IOOP
V
V
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
V
L
1.67
1.71
1.68
1.68
(1)(2)
0
0
0
– 1.00
– 0.75
-1
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
0.99
-2
Speed Grade
Virtex-6 CXT Family Data Sheet
V
V
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
V
V
V
V
V
1.67
1.71
1.68
1.68
REF
REF
REF
REF
REF
REF
REF
V
-2
Speed Grade
H
2.5
1.8
1.5
(1)(2)
+ 1.00
+ 0.75
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
T
IOTP
0.99
-1
1.67
1.71
1.68
1.68
-1
V
(1,4,5)
V
V
V
V
V
V
V
1.25
0.75
MEAS
0
0
0
0.9
REF
REF
REF
REF
REF
REF
REF
(6)
(6)
(6)
Figure
Units
Units
(1,3,5)
ns
V
ns
ns
ns
ns
0.75
0.90
0.90
1.08
1.25
0.90
1.5
REF
–
–
–
–
–
–
14.
REF
29