XC5VSX35T-2FFG665I Xilinx Inc, XC5VSX35T-2FFG665I Datasheet - Page 58
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XC5VSX35T-2FFG665I
Manufacturer Part Number
XC5VSX35T-2FFG665I
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-2FFG665I
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 2: Clock Management Technology
DCM Attributes
58
CLKDV_DIVIDE Attribute
CLKFX_MULTIPLY and CLKFX_DIVIDE Attribute
CLKIN_PERIOD Attribute
A handful of DCM attributes govern the DCM functionality.
applicable DCM attributes. This section provides a detailed description of each attribute.
For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to
the Constraints Guide at:
http://www.support.xilinx.com/support/software_manuals.htm.
The CLKDV_DIVIDE attribute controls the CLKDV frequency. The source clock frequency
is divided by the value of this attribute. The possible values for CLKDV_DIVIDE are: 1.5,
2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16. The default value is 2.
In the low frequency mode, any CLKDV_DIVIDE value produces a CLKDV output with a
50/50 duty-cycle. In the high frequency mode, the CLKDV_DIVIDE value must be set to
an integer value to produce a CLKDV output with a 50/50 duty-cycle. For non-integer
CLKDV_DIVIDE values, the CLKDV output duty cycle is shown in
Table 2-5: Non-Integer CLKDV_DIVIDE
The CLKFX_MULTIPLY attribute sets the multiply value (M) of the CLKFX output. The
CLKFX_DIVIDE attribute sets the divisor (D) value of the CLKFX output. Both control the
CLKFX output making the CLKFX frequency equal the effective CLKIN (source clock)
frequency multiplied by M/D. The possible values for M are any integer from two to 33.
The possible values for D are any integer from 1 to 32. The default settings are M = 4 and
D = 1.
The CLKIN_PERIOD attribute specifies the source clock period (in nanoseconds). The
default value is 0.0 ns. Setting this attribute to the input period values produces the best
results.
CLKDV_DIVIDE Value
1.5
2.5
3.5
4.5
5.5
6.5
7.5
www.xilinx.com
(High Pulse/Low Pulse Value)
High Frequency Mode
CLKDV Duty Cycle in
5/11
6/13
7/15
1/3
2/5
3/7
4/9
Table 2-6
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table
summarizes all the
2-5.
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