XC5VSX35T-2FFG665I Xilinx Inc, XC5VSX35T-2FFG665I Datasheet - Page 81
![IC FPGA VIRTEX-5 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-2FFG665I
Manufacturer Part Number
XC5VSX35T-2FFG665I
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-2FFG665I
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DCM with PLL
The PLL can be used to drive the DCM to reduce the source clock’s incoming jitter before
inputting DCM. This setup reduces the source clock jitter while enabling user access to all
available DCM clock outputs.
same CMT block using the dedicated routing resource (without BUFG).
X-Ref Target - Figure 2-14
IBUFG
www.xilinx.com
Figure 2-14: PLL Driving DCM
Figure 2-14
CLKIN1
CLKFBIN
RST
CLKIN
CLKFBIN
RST
illustrates the PLL driving a DCM within the
DCM
PLL
CLKFBOUT
CLKFX180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
CLK0
BUFG
BUFG
ug190_2_15_040906
Application Examples
81
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