XC5VSX50T-1FF1136C Xilinx Inc, XC5VSX50T-1FF1136C Datasheet - Page 328
XC5VSX50T-1FF1136C
Manufacturer Part Number
XC5VSX50T-1FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136C
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
52224
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
480
Ram Bits
4866048
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
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Chapter 7: SelectIO Logic Resources
328
Module Reset - RST
The IODELAY reset signal, RST, resets the delay element to a value set by the
IDELAY_VALUE or ODELAY_VALUE attribute. If these attributes are not specified, a
value of zero is assumed. The RST signal is an active-High reset and is synchronous to the
input clock signal (C).
The control pins are summarized in
Table 7-8: Control Pin Descriptions
Increment/Decrement Signals - CE, INC
The increment/decrement is controlled by the enable signal (CE). This interface is only
available for the IDELAY mode, when IDELAY_TYPE = VARIABLE.
As long as CE remains High, IDELAY will increment or decrement by T
every clock (C) cycle. The state of INC determines whether IDELAY will increment or
decrement; INC = 1 increments, INC = 0 decrements, synchronously to the clock (C). If CE
is Low the delay through IDELAY will not change regardless of the state of INC.
When CE goes High, the increment/decrement operation begins on the next positive clock
cycle. When CE goes Low, the increment/decrement operation ceases on the next positive
clock cycle.
IODELAY is a wrap-around programmable delay element. When the end of the delay
element is reached (tap 63) a subsequent increment function will return to tap 0. The same
applies to the decrement function: decrementing below zero moves to tap 63. The
increment/decrement operation is summarized in
Table 7-9: Increment/Decrement Operations
Notes:
1. RST takes precedence over CE and INC.
Reset to IDELAY_VALUE
Increment tap count
Decrement tap count
No change
INC
RST
Pin
CE
Input
Input
Input
Type
Operation
www.xilinx.com
Value
1
1
1
Table
Increment/decrement number of tap delays
Enable increment/decrement function
Reset delay element to pre-programmed value. If no
value programmed, reset to 0
7-8.
Table
RST
1
0
0
0
Description
7-9.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CE
x
1
1
0
IDELAYRESOLUTION
INC
x
1
0
x
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