XC5VLX110-1FF1760C Xilinx Inc, XC5VLX110-1FF1760C Datasheet - Page 297
XC5VLX110-1FF1760C
Manufacturer Part Number
XC5VLX110-1FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
XC5VLX110-1FF1760C
Manufacturer:
Xilinx Inc
Quantity:
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
LVPECL Transceiver Termination
LVPECL is a very popular and powerful high-speed interface in many system applications.
Virtex-5 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for
2.5V LVPECL to make system and board design easier.
The Virtex-5 FPGA LVPECL transmitter and receiver requires the termination shown in
Figure
50 Ω transmission lines. The LVPECL driver is composed of two LVCMOS drivers that
form a compliant LVPECL output when combined with the three resistor output
termination circuit.
X-Ref Target - Figure 6-90
LVPECL_25
LVPECL_25
6-90, illustrating a Virtex-5 FPGA LVPECL transmitter and receiver on a board with
IOB
Figure 6-90: LVPECL Transmitter Termination
www.xilinx.com
70Ω
70Ω
R
R
S
S
R DIV
187Ω
Specific Guidelines for I/O Supported Standards
Z 0 = 50Ω
Z 0 = 50Ω
R DIFF = 100Ω
INX
IN
IOB
LVPECL_25
+
-
ug190_6_84_030506
Data in
297
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