XC5VLX110-1FF1760C Xilinx Inc, XC5VLX110-1FF1760C Datasheet - Page 85
XC5VLX110-1FF1760C
Manufacturer Part Number
XC5VLX110-1FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-1FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Fixed-Phase Shifting
In
in phase with the desired clock phase. The clock outputs are phase-shifted to appear
sometime later than the input clock, and the LOCKED signal is asserted.
X-Ref Target - Figure 2-18
•
Figure
Clock Event 1
Clock event 1 appears after the desired phase shifts are applied to the DCM. In this
example, the shifts are positive shifts. CLK0 and CLK2X are no longer aligned to
CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and
CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted
once the clock outputs are ready.
2-18, the DCM outputs the correct frequency. However, the clock outputs are not
LOCKED
CLK180
CLK2X
CLK90
CLKIN
CLK0
Figure 2-18: Phase Shift Example: Fixed
www.xilinx.com
Lock Time
1
ug190_2_19_042406
DCM Timing Models
85
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