XC5VSX50T-2FFG665I Xilinx Inc, XC5VSX50T-2FFG665I Datasheet - Page 63
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XC5VSX50T-2FFG665I
Manufacturer Part Number
XC5VSX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-2FFG665I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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DCM Design Guidelines
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Deskew
Clock Deskew Operation
This section provides a detailed description on using the Virtex-5 FPGA DCM and design
guidelines.
The Virtex-5 FPGA DCM offers a fully digital, dedicated, on-chip clock deskew. The
deskew feature provides zero propagation delay between the source clock and output
clock, low clock skew among output clock signals distributed throughout the device, and
advanced clock domain control.
The deskew feature also functions as a clock mirror of a board-level clock serving multiple
devices. This is achieved by driving the CLK0 output off-chip to the board (and to other
devices on the board) and then bringing the clock back in as a feedback clock. See the
Application Examples
and improves system-level design involving high-fanout, high-performance clocks.
The deskew feature utilizes the DLL circuit in the DCM. In its simplest form, the DLL
consists of a single variable delay line (containing individual small delay elements or
buffers) and control logic. The incoming clock drives the delay line. The output of every
delay element represents a version of the incoming clock (CLKIN) delayed at a different
point. The clock distribution network routes the clock to all internal registers and to the
clock feedback CLKFB pin. The control logic contains a phase detector and a delay-line
selector. The phase detector compares the incoming clock signal (CLKIN) against a
feedback input (CLKFB) and steers the delay-line selector, essentially adding delay to the
DCM output until the CLKIN and CLKFB coincide, putting the two clocks 360° out-of-
phase, (thus, in phase). When the edges from the input clock line up with the edges from
the feedback clock, the DCM achieves a lock. The two clocks have no discernible
difference. Thus, the DCM output clock compensates for the delay in the clock distribution
network, effectively removing the delay between the source clock and its loads. The size of
each intrinsic delay element is a DCM_TAP (see the AC Characteristics table in the Virtex-5
FPGA Data Sheet).
X-Ref Target - Figure 2-3
To provide the correct clock deskew, the DCM depends on the dedicated routing and
resources used at the clock source and feedback input. An additional delay element (see
Deskew
Xilinx ISE tools analyze the routing around the DCM to determine if a delay must be
inserted to compensate for the clock source or feedback path. Thus, using dedicated
routing is required to achieve predictable deskew.
Adjust) is available to compensate for the clock source or feedback path. The
CLKIN
Figure 2-3
section. Taking advantage of the deskew feature greatly simplifies
www.xilinx.com
Figure 2-3: Simplified DLL Circuit
illustrates a simplified DLL circuit.
Control
Delay Line
Variable
CLKFB
CLKOUT
Distribution
Network
Clock
ug190_2_03_032506
DCM Design Guidelines
63
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