XC5VLX85-2FFG676I Xilinx Inc, XC5VLX85-2FFG676I Datasheet - Page 125
![IC FPGA VIRTEX-5 85K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX85-2FFG676I
Manufacturer Part Number
XC5VLX85-2FFG676I
Description
IC FPGA VIRTEX-5 85K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-2FFG676I
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Block RAM Port Signals
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock - CLK[A|B]
Enable - EN[A|B]
Byte-wide Write Enable - WE[A|B]
Register Enable - REGCE[A|B]
Set/Reset - SSR[A|B]
Address Bus - ADDR[A|B]<13:#><14:#><15:#>
Each block RAM port operates independently of the other while accessing the same set of
36K-bit memory cells.
Each port is fully synchronous with independent clock pins. All port input pins have setup
time referenced to the port CLK pin. The output data bus has a clock-to-out time
referenced to the CLK pin. Clock polarity is configurable (rising edge by default).
The enable pin affects the read, write, and set/reset functionality of the port. Ports with an
inactive enable pin keep the output pins in the previous state and do not write data to the
memory cells. Enable polarity is configurable (active High by default).
To write the content of the data input bus into the addressed memory location, both EN
and WE must be active within a set-up time before the active clock edge. The output
latches are loaded or not loaded according to the write configuration (WRITE_FIRST,
READ_FIRST, NO_CHANGE). When inactive, a read operation occurs, and the contents of
the memory cells referenced by the address bus appear on the data-out bus, regardless of
the write mode attribute. Write enable polarity is not configurable (active High).
The register enable pin (REGCE) controls the optional output register. When the RAM is in
register mode, REGCE = 1 registers the output into a register at a clock edge. The polarity
of REGCE is not configurable (active High).
In latch mode, the SSR pin forces the data output latches, to contain the value SRVAL. See
Block RAM Attributes, page
output registers can also be forced by the SSR pin to contain the value SRVAL. SSR does not
affect the latched value. The data output latches or output registers are synchronously
asserted to 0 or 1, including the parity bit. Each port has an independent SRVAL[A|B]
attribute of 36 bits. This operation does not affect RAM memory cells and does not disturb
write operations on the other port. Similar to the read and write operation, the set/reset
function is active only when the enable pin of the port is active. Set/reset polarity is
configurable (active High by default).
The address bus selects the memory cells for read or write. The data bit width of the port
determines the required address bus width for a single RAMB18 or RAMB36, as shown in
Table 4-6
and
Table
4-7.
www.xilinx.com
128. When the optional output registers are enabled, the data
Block RAM Port Signals
125
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