XC5VLX85-2FFG676I Xilinx Inc, XC5VLX85-2FFG676I Datasheet - Page 55
![IC FPGA VIRTEX-5 85K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX85-2FFG676I
Manufacturer Part Number
XC5VLX85-2FFG676I
Description
IC FPGA VIRTEX-5 85K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85-2FFG676I
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3538944
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1x Output Clock, 90° Phase Shift - CLK90
1x Output Clock, 180° Phase Shift - CLK180
1x Output Clock, 270° Phase Shift - CLK270
2x Output Clock - CLK2X
2x Output Clock, 180° Phase Shift - CLK2X180
Frequency Divide Output Clock - CLKDV
Frequency-Synthesis Output Clock - CLKFX
Frequency-Synthesis Output Clock, 180° - CLKFX180
The CLK90 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 90°.
The CLK180 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 180°.
The CLK270 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 270°.
The CLK2X output clock provides a clock that is phase aligned to CLK0, with twice the
CLK0 frequency, and with an automatic 50/50 duty-cycle correction. Until the DCM is
locked, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty
cycle. This behavior allows the DCM to lock on the correct edge with respect to the source
clock.
The CLK2X180 output clock provides a clock with the same frequency as the DCM’s
CLK2X phase-shifted by 180°.
The CLKDV output clock provides a clock that is phase aligned to CLK0 with a frequency
that is a fraction of the effective CLKIN frequency. The fraction is determined by the
CLKDV_DIVIDE attribute. Refer to the
The CLKFX output clock provides a clock with the following frequency definition:
In this equation, M is the multiplier (numerator) with a value defined by the
CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the
CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output
frequency ranges for the frequency synthesizer, are provided in the Virtex-5 FPGA Data
Sheet.
The rising edge of CLKFX output is phase aligned to the rising edges of CLK0, CLK2X, and
CLKDV. When M and D to have no common factor, the alignment occurs only once every
D cycles of CLK0.
The CLKFX180 output clock provides a clock with the same frequency as the DCM’s
CLKFX phase-shifted by 180°.
CLKFX frequency = (M/D) × effective CLKIN frequency
www.xilinx.com
CLKDV_DIVIDE Attribute
for more information.
DCM Ports
55
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