XCV812E-6FG900C Xilinx Inc, XCV812E-6FG900C Datasheet - Page 43
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XCV812E-6FG900C
Manufacturer Part Number
XCV812E-6FG900C
Description
IC FPGA 1.8V C-TEMP 900-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-E EMr
Datasheet
1.XCV405E-6FG676C.pdf
(118 pages)
Specifications of XCV812E-6FG900C
Number Of Logic Elements/cells
21168
Number Of Labs/clbs
4704
Total Ram Bits
1146880
Number Of I /o
556
Number Of Gates
254016
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
900-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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Company:
Part Number:
XCV812E-6FG900C
Manufacturer:
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20 000
Input termination techniques include the following:
•
•
These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 21
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to
power/ground pairs for each Virtex-E device and package
combination.
DS025-2 (v2.3) November 19, 2002
Figure 43: Overview of Standard Input and Output
None
Parallel (Shunt)
provides the guidelines for the maximum number
Unterminated Output Driving
Table 22
a Parallel Terminated Input
Series Terminated Output
R
Unterminated
Z=50
Z=50
Z=50
Termination Methods
V
V
REF
REF
for the number of effective output
V
TT
Figure
43.
Driving a Parallel Terminated Input
Series-Parallel Terminated Output
Series Terminated Output Driving
Double Parallel Terminated
a Parallel Terminated Input
V
V
TT
TT
Z=50
Z=50
Z=50
V
REF
V
V
REF
REF
V
TT
V
V
x133_07_111699
TT
TT
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Table 21:
Table 22:
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS
PCI
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
AGP
Note: This analysis assumes a 35 pF load for each output.
Pkg/Part
BG560
FG676
FG900
Guidelines for Maximum Number of
Simultaneously Switching Outputs per
Power/Ground Pair
Virtex-E Extended Memory Family
Equivalent Power/Ground Pairs
Standard
XCV405E
56
BGA, FGA
Package
XCV812E
Module 2 of 4
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22
17
14
40
24
17
13
10
10
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8
4
4
9
5
7
9
56
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