XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 83
![IC FPGA VIRTEX-5 110K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-1FFG1136C
Manufacturer Part Number
XC5VLX110T-1FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-1FFG1136C
Total Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
640
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VLX110T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 83 of 385
- Download datasheet (14Mb)
VHDL and Verilog Templates, and the Clocking Wizard
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 2-16
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives. In addition, VHDL and Verilog files are generated by the Clocking Wizard in
the ISE software. The Clocking Wizard sets appropriate DCM attributes, input/output
clocks, and buffers for general use cases.
IBUFG
IBUFG
Figure 2-16: Two DCMs Driving a PLL
www.xilinx.com
VHDL and Verilog Templates, and the Clocking Wizard
CLKIN1
CLKIN2
CLKFBIN
RST
CLKIN
CLKFBIN
CLKIN
CLKFBIN
RST
DCM1
DCM
PLL
CLKFBOUT
CLKFX180
CLKFX180
CLK2X180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLKFX
CLKFX
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
BUFG
BUFG
BUFG
BUFG
BUFG
ug190_2_18_040906
83
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