XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 90

IC FPGA VIRTEX-5 110K 1136FBGA

XC5VLX110T-1FFG1136C

Manufacturer Part Number
XC5VLX110T-1FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX110T-1FFG1136C

Total Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
640
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX110T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX110T-1FFG1136C
Manufacturer:
XILINX
0
Part Number:
XC5VLX110T-1FFG1136C
0
Part Number:
XC5VLX110T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Chapter 3: Phase-Locked Loops (PLLs)
X-Ref Target - Figure 3-1
90
From any IBUFG implementation
From any BUFG implementation
Phase Locked Loop (PLL)
Virtex-5 devices contain up to six CMT tiles. The PLLs main purpose is to serve as a
frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for
either external or internal clocks in conjunction with the DCMs of the CMT.
The PLL block diagram shown in
components.
X-Ref Target - Figure 3-2
Clock Pin
Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT
Figure 3-2: Block Diagram of the Virtex-5 FPGA PLL
D
www.xilinx.com
PFD
Figure 3-2
DCM1
DCM2
PLL
M
CP
provides a general overview of the PLL
LF
clkout_pll<5:0>
VCO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
To any BUFG
implementation
To any BUFG
implementation
To any BUFG
implementation
UG190_c3_01_022709
O0
O1
O2
O3
O4
O5
ug190_3_02_030506

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