XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet - Page 73

• Manufacturer Part Number: XCV812E-7FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-7FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
DS025-3 (v2.3.2) March 14, 2003
Notes:
1.
2.
3.
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time
delay by the values shown in
Characteristics Standard Adjustments’’ on page
No Delay
Global Clock and IFF, with DLL
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time delay
by the values shown in
Standard Adjustments’’ on page
Full Delay
Global Clock and IFF, without DLL
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
Description
Description
R
(1)
(1)
‘‘IOB Input Switching Characteristics
‘‘IOB Input Switching
6.
T
PSDLL
Symbol
T
PSFD
Symbol
/T
PHDLL
/T
PHFD
6.
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
XCV405E
XCV812E
Device
XCV405E
XCV812E
Device
(3)
(3)
1.5 / –0.4
1.5 / –0.4
Min
2.3 / 0
2.5 / 0
Min
1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
Speed Grade
2.3 / 0
2.5 / 0
-8
Speed Grade
-8
2.3 / 0
2.5 / 0
-7
-7
(2)
(2)
2.3 / 0
2.5 / 0
-6
-6
Module 3 of 4
Units
Units
ns
ns
ns
ns
17