XC5VLX110T-3FFG1136C Xilinx Inc, XC5VLX110T-3FFG1136C Datasheet - Page 322
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XC5VLX110T-3FFG1136C
Manufacturer Part Number
XC5VLX110T-3FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FFG1136C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-3FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
322
IDDR VHDL and Verilog Templates
ILOGIC Timing Models
ILOGIC Timing Characteristics
Table 7-4: IDDR Attributes
The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL
and Verilog.
This section describes the timing associated with the various resources within the ILOGIC
block.
Figure 7-6
T
X-Ref Target - Figure 7-6
Clock Event 1
•
•
DDR_CLK_EDGE
INIT_Q1
INIT_Q2
SRTYPE
CLK
CE1
IDOCKD
SR
Q1
Attribute Name
D
At time T
High at the CE1 input of the input register, enabling the input register for incoming
data.
At time T
input of the input register and is reflected on the Q1 output of the input register at
time T
.
illustrates ILOGIC register timing. When IDELAY is used, T
ICKQ
ICE1CK
IDOCK
Figure 7-6: ILOGIC Input Register Timing Characteristics
after Clock Event 1.
1
before Clock Event 1, the input signal becomes valid-High at the D
before Clock Event 1, the input clock enable signal becomes valid-
Sets the IDDR mode of operation with
respect to clock edge
Sets the initial value for Q1 port
Sets the initial value for Q2 port
Set/Reset type with respect to clock (C) ASYNC (default), SYNC
T
T
IDOCK
ICE1CK
www.xilinx.com
T
ICKQ
Description
2
3
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Possible Values
T
ISRCK
IDOCK
T
ICKQ
is replaced by
ug190_7_06_041206
5
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