XC5VLX110T-3FFG1136C Xilinx Inc, XC5VLX110T-3FFG1136C Datasheet - Page 99
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XC5VLX110T-3FFG1136C
Manufacturer Part Number
XC5VLX110T-3FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FFG1136C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-3FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 3-4: PLL Attributes (Continued)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIVCLK_DIVIDE
CLKFBOUT_PHASE
REF_JITTER
CLKIN1_PERIOD
CLKIN2_PERIOD
CLKOUT[0:5]_
DESKEW_ADJUST
RESET_ON_LOSS
_OF_LOCK
Attribute
Integer
String
String
Type
Real
Real
Real
Real
Allowed Values
1.408 to 52.630
1.408 to 52.630
0.000 to 0.999
PPC or None
0.0 to 360.0
FALSE
1 to 52
www.xilinx.com
Default
FALSE
None
0.100
0.000
0.000
0.0
1
Specifies the division ratio for all
output clocks with respect to the
input clock.
Specifies the phase offset in
degrees of the clock feedback
output. Shifting the feedback clock
results in a negative phase shift of
all output clocks to the PLL.
Allows specification of the
expected jitter on the reference
clock in order to better optimize
PLL performance. A bandwidth
setting of OPTIMIZED will
attempt to choose the best
parameter for input clocking
when unknown. If known, then
the value provided should be
specified in terms of the UI
percentage (the maximum peak to
peak value) of the expected jitter
on the input clock.
Specifies the input period in ns to
the PLL CLKIN1 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
Specifies the input period in ns to
the PLL CLKIN2 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
Fixed delay used when the PLL is
used in a PPC440 system.
See UG200: Embedded Processor
Block in Virtex-5 FPGAs Reference
Guide for details.
Must be set to FALSE, not
supported in silicon.
General Usage Description
Description
99
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