AT40K20-2AQC Atmel, AT40K20-2AQC Datasheet - Page 6

• Manufacturer Part Number: AT40K20-2AQC
• Description: IC FPGA 20K GATES 100TQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K20-2AQC

• Number Of Logic Elements/cells: 1024
• Total Ram Bits: 8192
• Number Of I /o: 78
• Number Of Gates: 30000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K202AQC

The Busing Network
6
AT40K/AT40KLV Series FPGA
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regener-
ate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programma-
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface. Express/Express turns are
implemented through separate pass gates distributed throughout the array.
Some of the bus resources on the AT40K/AT40KLV are used as a dual-function
resources. Table 2 shows which buses are used in a dual-function mode and which bus
plane is used. The AT40K/AT40KLV software tools are designed to accommodate dual-
function buses in an efficient manner.
Table 2. Dual-function Buses
Function
Cell Output Enable
RAM Output Enable
RAM Write Enable
RAM Address
RAM Data In
RAM Data Out
Clocking
Set/Reset
Type
Local
Express
Express
Local
Local
Express
Express
Express
Plane(s)
1 - 5
5
2
1
1
2
4
5
Direction
Horizontal
and Vertical
Vertical
Vertical
Vertical
Horizontal
Horizontal
Vertical
Vertical
Comments
Bus full length at array edge
Bus in first column to left of
RAM block
Bus full length at array edge
Bus in first column to left of
RAM block
Buses full length at array edge
Buses in second column to left
of RAM block
Data In connects to local
bus plane 1
Data out connects to local
bus plane 2
Bus half length at array edge
Bus half length at array edge
0896C–FPGA–04/02