AT6002LV-4JC Atmel, AT6002LV-4JC Datasheet
AT6002LV-4JC
Specifications of AT6002LV-4JC
Related parts for AT6002LV-4JC
AT6002LV-4JC Summary of contents
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... Open Collector/Tristate Outputs – Programmable Slew-rate Control – I/O Drive (combinable to 64 mA) • Easy Migration to Atmel Gate Arrays for High Volume Production Description AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute-intensive logic. ...
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... Figure 1. Symmetrical Array Surrounded by I/O AT6000(LV) Series 2 The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous and completely uninterrupted from one edge to the other, except for bus repeaters spaced every eight cells (Figure 2). ...
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Figure 2. Busing Network (one sector) Figure 3. Cell-to-cell and Bus-to-bus Connections AT6000(LV) Series CELL REPEATER 3 ...
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... This option is primarily used to imple- ment long, tristate buses. The Cell Structure The Atmel cell (Figure 4) is simple and small and yet can be programmed to perform all the logic and wiring functions needed to implement any digital circuit. Its four sides are functionally identical, so each cell is completely symmetrical. Read/write access to the four local buses – ...
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... The AND of the outputs from the two upstream AND gates is provided to the cell's B output. Logic States The Atmel cell implements a rich and powerful set of logic functions, stemming from 44 logical cell states which per- mutate into 72 physical states. Some states use both A and B inputs. Other states are created by selecting the “ ...
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Figure 5. Combinatorial Physical States ...
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... GLOBAL CLOCK with registers requiring no reset. All registers are reset dur- ing power-up. Input/Output The Atmel architecture provides a flexible interface EXPRESS between the logic array, the configuration control logic and BUS the I/O pins. Two adjacent cells – an “exit” and an “entrance” cell – on ...
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Figure 11. A-type I/O Logic Figure 12. B-type I/O Logic TTL/CMOS Inputs A user-configurable bit determines the threshold level – TTL or CMOS – of the input buffer. Open Collector/Tristate Outputs A user-configurable bit which enables or disables the active ...
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The devices can be partially reconfigured while in opera- tion. Portions of the device not being modified remain operational during reconfiguration. Simultaneous configu- ration of more than one device is also possible. Full configuration takes as little as a millisecond, ...
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FPGA. Addresses change after the rising edge of the CCLK signal. CSOUT or I/O When cascading devices, CSOUT is an output used to enable other devices. CSOUT should be connected to the CS input of the ...
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Pinout Assignment AT6002 AT6003 AT6005 - - - I/O24( I/O30( I/O27( I/O29( I/O28(A) I/O26(A) I/O23( I/O27(A) or ...
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Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O9(B) I/O11(B) I/O10( I/O8( I/O10( I/O9( I/O7(B) I/O9(B) I/O8( I/O6( I/O8( I/O7( ...
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Pinout Assignment AT6002 AT6003 AT6005 CON CON CON - - - I/O96(A) I/O120(A) I/O108(A) - I/O119( I/O118(A) I/O107(A) I/O95(A) or I/O117(A) or I/O106(A) or CSOUT CSOUT ...
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Pinout Assignment (Continued) AT6002 AT6003 AT6005 - - - VCC VCC VCC I/O82(A) I/O102(A) I/O92(A) I/O81(B) I/O101(B) I/O91( I/O80(A) I/O100(A) I/O90(A) I/O79(B) I/O99(B) I/O89( I/O78(A) I/O98(A) I/O88(A) - I/O97(B) I/O87(A) - ...
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Pinout Assignment AT6002 AT6003 AT6005 - - - I/O72(A) I/O90(A) I/O81(A) - I/O89(B) I/O80( I/O88(A) - I/O71(A) I/O87(A) I/O79( I/O70(B) I/O86(A) ...
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Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O57(B) I/O71(B) I/O64( I/O56(A) I/O70(A) I/O63(A) I/O55(B) I/O69(B) I/O62( I/O54(A) I/O68(A) I/O61(A) - I/O67(B) I/O60( GND GND GND - - - - ...
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Pinout Assignment AT6002 AT6003 AT6005 I/O48(A) I/O60(A) I/O54(A) - I/O59( I/O58(A) I/O53(A) I/O47(A) I/O57(A) I/O52( ...
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Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O34(A) or A13 I/O42(A) or A13 I/O38(A) or A13 I/O33(B) I/O41(B) I/O37( I/O32(A) or A12 I/O40(A) or A12 I/O36(A) or A12 I/O31(B) I/O39(B) I/O35( I/O30(A) ...
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... Buffer delay pad voltage of 1.5V with one output switching. 4. Max specifications are the average of mas t 5. Parameter based on characterization and simulation; not tested in production 6. Exact power calculation is available in an Atmel application note. 7. Load Definition Load of one input Load of one L input Constant Load Tester Load of 50 pF. = Preliminary Information ...
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... Max specifications are the average of mas t 5. Parameter based on characterization and simulation; not tested in production 6. Exact power calculation is available in an Atmel application note. 7. Load Definition Load of one input Load of one L input Constant Load Load of 28 Clock Columns Load of 28 Reset Columns Tester Load of 50 pF. ...
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Absolute Maximum Ratings* Supply Voltage (V ) ........................................-0. 7. Input Voltage (V ) ...............................-0. Output Voltage (V ) ...........................-0. Storage Temperature Range (TSTG)........................................................... -65°C to +150°C Power Dissipation (PD)............................................. ...
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DC Characteristics – 5V Operation Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL High-level Tristate I OZH Output Leakage Current High-level Tristate I OZL Output Leakage ...
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DC Characteristics – 3.3V Operation Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL High-level Tristate I OZH Output Leakage Current High-level Tristate I OZL Output Leakage ...
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... AT6002A-2AI AT6002-2JI AT6002-2QI 6,000 4 AT6002-4AC AT6002A-4AC AT6002-4JC AT6002-4QC AT6002LV-4AC AT6002ALV-4AC AT6002LV-4JC AT6002LV-4QC AT6002-4AI AT6002A-4AI AT6002-4JI AT6002-4QI 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100A 100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP) 132Q 132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP) 144A 144-lead, Thin (1 ...
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Ordering Information – AT6003 Usable Speed Gates Grade (ns) Ordering Code 9,000 2 AT6003-2AC AT6003A-2AC AT6003-2JC AT6003-2QC AT6003-2AI AT6003A-2AI AT6003-2JI AT6003-2QI 9,000 4 AT6003-4AC AT6003A-4AC AT6003-4JC AT6003-4QC AT6003LV-4AC AT6003ALV-4AC AT6003LV-4JC AT6003LV-4QC AT6003-4AI AT6003A-4AI AT6003-4JI AT6003-4QI 84J 84-lead, Plastic J-leaded Chip ...
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Ordering Information – AT6005 Usable Speed Gates Grade (ns) Ordering Code 15,000 2 AT6005-2AC AT6005A-2AC AT6005-2JC AT6005-2QC AT6005A-2QC AT6005-2AI AT6005A-2AI AT6005-2JI AT6005-2QI AT6005A-2QI 15,000 4 AT6005-4AC AT6005A-4AC AT6005-4JC AT6005-4QC AT6005A-4QC AT6005LV-4AC AT6005ALV-4AC AT6005LV-4JC AT6005LV-4QC AT6005ALV-4QC AT6005-4AI AT6005A-4AI AT6005-4JI AT6005-4QI AT6005A-4QI ...
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Ordering Information – AT6010 Usable Speed Gates Grade (ns) Ordering Code 30,000 2 AT6010-2JC AT6010A-2AC AT6010-2QC AT6010A-2QC AT6010H-2QC AT6010-2JI AT6010A-2AI AT6010-2QI AT6010A-2QI AT6010H-2QI 30,000 4 AT6010A-4AC AT6010-4QC AT6010-4JC AT6010A-4QC AT6010H-4QC AT6010ALV-4AC AT6010LV-4QC AT6010LV-4JC AT6010ALV-4QC AT6010HLV-4QC AT6010A-4AI AT6010-4QI AT6010-4JI AT6010A-4QI AT6010H-4QI ...
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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...