XC4013XL-1PQ240I Xilinx Inc, XC4013XL-1PQ240I Datasheet - Page 14

• Manufacturer Part Number: XC4013XL-1PQ240I
• Description: IC FPGA I-TEMP 3.3V 1SPD 240PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4013XL-1PQ240I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 192
• Number Of Gates: 13000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
6-86
Clocks
Clock High
Clock Low
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
Slew Rate Adjustment
For output SLOW option add
Note: Output timing is measured at ~50% V
* Indicates Minimum Amount of Time to Assure Valid Data.
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Description
CC
threshold, with 50 pF external capacitive loads.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
T
CH
CL
OKPOF
OPF
TSHZ
TSONF
OFPF
OKFPF
OOK
OKO
ECOK
OKEC
MRW
RPO*
SLOW
19.8
Min
3.0
3.0
0.5
0.0
0.0
0.3
-3
Max
14.3
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
5.0
4.1
4.0
4.4
5.5
5.1
3.0
DS005 (v. 1.8 October 18, 1999 - Product Specification
17.3
Min
2.8
2.8
0.4
0.0
0.0
0.2
-2
Max Min
12.5
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
4.3
3.6
3.5
3.8
4.8
4.5
2.5
15.0
2.5
2.5
0.3
0.0
0.0
0.1
-1
Max
10.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
3.8
3.1
3.0
3.3
4.2
3.9
2.0
14.0
Min
2.3
2.3
0.3
0.0
0.0
0.0
All devices are 100%
-09
1.7
Max
10.3
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
3.5
3.0
2.9
3.3
4.0
3.7
14.0
Min
2.1
2.1
0.3
0.0
0.0
0.0
-08
1.6
Max
14.0
19.3
23.5
3.3
2.8
2.9
3.3
3.7
3.4
R