XC4013XL-1PQ240I Xilinx Inc, XC4013XL-1PQ240I Datasheet - Page 7
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XC4013XL-1PQ240I
Manufacturer Part Number
XC4013XL-1PQ240I
Description
IC FPGA I-TEMP 3.3V 1SPD 240PQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Specifications of XC4013XL-1PQ240I
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
192
Number Of Gates
13000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
DS005 (v. 1.8 October 18, 1999 - Product Specification
Dual Port RAM
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Single-Port RAM
DATA OUT
ADDRESS
WCLK (K)
DATA IN
WE
R
T
ILO
T
T
T
WSS
DSS
ASS
OLD
XC4000E and XC4000X Series Field Programmable Gate Arrays
T
T
T
WOS
T
DHS
WHS
AHS
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Size
Speed Grade
T
WPS
NEW
T
ILO
T
T
T
T
T
T
T
T
T
Symbol Min Max Min Max Min Max Min Max Min Max
WCDS
WPDS
ASDS
AHDS
DSDS
DHDS
WSDS
WHDS
WODS
X6461
9.0
4.5
2.5
2.5
1.8
0
0
0
DATA OUT
Dual-Port RAM
ADDRESS
WCLK (K)
DATA IN
-3
7.8
WE
8.4
4.2
2.0
2.3
1.7
0
0
0
-2
7.3
T
ILO
T
7.7
3.9
1.7
2.0
1.6
T
T
0
0
0
WSDS
DSDS
ASDS
--1
T
6.7
WODS
OLD
T
T
7.4
3.7
1.7
2.0
1.6
T
WHDS
0
0
0
DHDS
AHDS
All devices are 100%
-09
T
WPDS
6.7
NEW
T
ILO
7.4
3.7
1.6
2.0
1.6
0
0
0
X6474
-08
6.6
6-79
6