XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 310
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 310 of 385
- Download datasheet (14Mb)
Chapter 6: SelectIO Resources
310
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
2.5V
LVCMOS25_2_slow
LVCMOS25_4_slow
LVCMOS25_6_slow
LVCMOS25_8_slow
LVCMOS25_12_slow
LVCMOS25_16_slow
LVCMOS25_24_slow
LVCMOS25_2_fast
LVCMOS25_4_fast
LVCMOS25_6_fast
LVCMOS25_8_fast
LVCMOS25_12_fast
LVCMOS25_16_fast
LVCMOS25_24_fast
LVDCI_25 50 Ω
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
HSLVDCI_25 50 Ω
DIFF_SSTL_I
DIFF_SSTL_I_DCI
DIFF_SSTL_II
DIFF_SSTL_II_DCI
LVPECL_25
BLVDS_25
LVDS_25
LVDSEXT_25
RSDS_25
HT_25
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
20
20
20
20
20
20
20
20
20
20
20
20
20
15
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
30
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
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