XC5VSX35T-1FFG665CES Xilinx Inc, XC5VSX35T-1FFG665CES Datasheet - Page 29
![IC FPGA VIRTEX-5 ES 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-1FFG665CES
Manufacturer Part Number
XC5VSX35T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665CES
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX35T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- Current page: 29 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
BUFGCTRL is designed to switch between two clock inputs without the possibility of a
glitch. When the presently selected clock transitions from High to Low after S0 and S1
change, the output is kept Low until the other (to-be-selected) clock has transitioned from
High to Low. Then the new clock starts driving the output.The default configuration for
BUFGCTRL is falling edge sensitive and held at Low prior to the input switching.
BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching.
In some applications the conditions previously described are not desirable. Asserting the
IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching
between two clock inputs. In other words, asserting IGNORE causes the mux to switch the
inputs at the instant the select pin changes. IGNORE0 causes the output to switch away
from the I0 input immediately when the select pin changes, while IGNORE1 causes the
output to switch away from the I1 input immediately when the select pin changes.
Selection of an input clock requires a “select” pair (S0 and CE0, or S1 and CE1) to be
asserted High. If either S or CE is not asserted High, the desired input will not be selected.
In normal operation, both S and CE pairs (all four select lines) are not expected to be
asserted High simultaneously. Typically only one pin of a “select” pair is used as a select
line, while the other pin is tied High. The truth table is shown in
Table 1-3: Truth Table for Clock Resources
Although both S and CE are used to select a desired output, each one of these pins behaves
slightly different. When using CE to switch clocks, the change in clock selection can be
faster than when using S. Violation in Setup/Hold time of the CE pins causes a glitch at the
clock output. On the other hand, using the S pins allows the user to switch between the two
clock inputs without regard to Setup/Hold times. It will not result in a glitch. See
BUFGMUX_CTRL. The CE pin is designed to allow backward compatibility from Virtex-II
and Virtex-II Pro FPGAs.
Notes:
1. Old input refers to the valid input clock before this state is achieved.
2. For all other states, the output becomes the value of INIT_OUT and does not toggle.
CE0
X
1
1
0
1
S0
www.xilinx.com
X
1
1
0
1
CE1
X
0
1
1
1
Global Clocking Resources
S1
X
0
1
1
1
Table
1-3.
Old Input
O
I0
I0
I1
I1
(1)
29
Related parts for XC5VSX35T-1FFG665CES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![XC5VSX35T-1FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-1FF665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-X1FFG665C](/images/no-image3.png)
Part Number:
Description:
IC FPGA VIRTEX 5 35K 665FFGBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-2FF665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-2FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-1FF665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-1FFG665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-2FF665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-2FFG665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-3FF665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX35T-3FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC9536XL-10VQG44C](/photos/6/70/67071/xc9536xl-10vqg44c_tmb.jpg)
Part Number:
Description:
IC CPLD .8K 36MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC9572XL-10VQG44C](/photos/6/70/67078/xc9572xl-10vqg44c_tmb.jpg)
Part Number:
Description:
IC CPLD 72MCRCELL 10NS 44VQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC9572XL-10VQG64C](/photos/6/70/67079/xc9572xl-10vqg64c_tmb.jpg)
Part Number:
Description:
IC CPLD 1.6K 72MCELL 64-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XC2C64A-7VQG44C](/photos/6/70/67080/xc2c64a-7vqg44c_tmb.jpg)
Part Number:
Description:
IC CR-II CPLD 64MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet: