XC5VSX35T-1FFG665CES Xilinx Inc, XC5VSX35T-1FFG665CES Datasheet - Page 306
![IC FPGA VIRTEX-5 ES 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-1FFG665CES
Manufacturer Part Number
XC5VSX35T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665CES
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
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Company:
Part Number:
XC5VSX35T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 6: SelectIO Resources
306
Nominal PCB Specifications
PCB Construction
Signal Return Current Management
Load Traces
Power Distribution System Design
The nominal SSO table
parameters meet the following requirements.
Note:
SSO Calculator must be used to determine the SSO limit, according to the physical factors of the
unique PCB.
•
•
•
•
•
•
•
•
•
V
Total board thickness must be no greater than 62 mils (1575 µ).
Traces must be referenced to a plane on an adjacent PCB layer.
The reference plane must be either GND or the V
driver.
The reference layer must remain uninterrupted for its full length from device to
device.
All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ± 10%.
Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Designed according to the Virtex-5 FPGA PCB Designer’s Guide.
•
•
V
CCO
CCO
In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA
Decoupling capacitors per the device guideline
Approved solder land patterns
and GND vias should have a drill diameter no less than 11 mils (279 µ).
and GND planes cannot be separated by more than 5.0 mils (152 µ)
(Table
www.xilinx.com
6-40) contains SSO limits for cases where the PCB
CCO
associated with the output
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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