CY8CTST200-16LGXI Cypress Semiconductor Corp, CY8CTST200-16LGXI Datasheet - Page 275
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CY8CTST200-16LGXI
Manufacturer Part Number
CY8CTST200-16LGXI
Description
IC MCU 32K FLASH 16-QFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-16LGXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
13
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-QFN
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2973
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8CTST200-16LGXI
Manufacturer:
CY
Quantity:
1 300
Part Number:
CY8CTST200-16LGXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
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21.4.16 IO_CFG2
The Input/Output Configuration 2 Register (IO_CFG2) selects output regulated supply and clock rates.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
GPIO chapter.
Bits
5:3
1:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
IO_CFG2 : 1,DEh
Access : POR
Bit Name
Name
REG_LEVEL[2:0]
REG_CLOCK[1:0]
Input/Output Configuration Register 2
7
6
Description
These bits select output regulated supply
The Regulated I/O charge pump can operate with a maximum clock speed of 12 MHZ. The
REG_CLOCK[1:0] bits select clocking options for the regulator. Setting REG_CLOCK[1:0] to ‘10’
should be used with 24 MHz SYSCLK and ‘01’ should be used with 6/12 MHz SYSCLK.
000
001
010
011
100
101
110
111
10
01
REG_LEVEL[2:0]
REG_CLOCK[1:0]
5
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
24 MHz
6/12 MHz
REG_LEVEL[2:0]
SYSCLK Clock Rate
Approx. Regulated Supply (V)
RW : 0
4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
IO_CFG2 Register on page 61
2
1,DEh
1
REG_CLOCK[1:0]
RW : 0
1,DEh
IO_CFG2
0
in the
275
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