CY7C66013C-PVXC Cypress Semiconductor Corp, CY7C66013C-PVXC Datasheet - Page 40

• Manufacturer Part Number: CY7C66013C-PVXC
• Description: IC MCU 8K USB HUB 4 PORT 48-SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013C-PVXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 29
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Controller Family/series: (8051) USB
• No. Of I/o's: 29
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2261-5; CY7C66013C-PVXC

USB Non Control Endpoint Mode Registers
The format of the non control endpoint mode registers is shown in
USB Non Control Device Endpoint Mode
Bits[3..0]: Mode
These sets the mode which control how the control endpoint
responds to traffic. The mode bit encoding is shown in
Bit 4: ACK
This bit is set whenever the SIE engages in a transaction to the
register’s endpoint that completes with an ACK packet.
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats for both control and non control endpoints. These registers contain
byte count information for USB transactions, and bits for data packet status. The format of these registers is shown in
USB Endpoint Counter
Bits[5..0]: Byte Count
These counter bits indicate the number of data bytes in a
transaction. For IN transactions, firmware loads the count with
the number of bytes to be transmitted to the host from the
endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or
SETUP transactions, the count is updated by hardware to the
number of data bytes received, plus two for the CRC bytes. Valid
values are 2 to 34, inclusive.
Bit 6: Data Valid
This bit is set on receiving a proper CRC when the endpoint FIFO
buffer is loaded with data during transactions. This bit is used
OUT and SETUP tokens only. If the CRC is not correct, the
endpoint interrupt occurs, but Data Valid is cleared to a zero.
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
7
Data 0/1
Toggle
R/W
0
STALL
7
R/W
0
6
Data Valid
R/W
0
6
Reserved
0
R/W
Figure 45. USB Non Control Endpoint Mode Registers
Figure 46. USB Endpoint Counter Registers
5
Byte Count
Bit 5
R/W
0
5
Reserved
R/W
0
Table
4
Byte Count
Bit 4
R/W
0
4
ACK
R/W
0
12.
Figure
Bits[6..5]: Reserved
Must be written zero during register writes.
Bit 7: STALL
If this STALL is set, the SIE stalls an OUT packet if the mode bits
are set to ACK-IN, and the SIE stalls an IN packet if the
mode bits are set to ACK-OUT. For all other modes, the STALL
bit must be a LOW.
Bit 7: Data 0/1 Toggle
This bit selects the DATA packet’s toggle state: 0 for DATA0, 1
for DATA1. For IN transactions, firmware must set this bit to the
desired state. For OUT or SETUP transactions, the hardware
sets this bit to the state of the received Data Toggle bit.
Whenever the count updates from a SETUP or OUT transaction
on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents
firmware from overwriting a status update on incoming SETUP
or OUT transactions before firmware has a chance to read the
data. Only endpoint 0 counter register is locked when updated.
The locking mechanism does not apply to the count registers of
other endpoints.
3
Byte Count
Bit 3
R/W
0
45.
3
Mode Bit 3
R/W
0
ADDRESSES
CY7C66013C, CY7C66113C
2
Byte Count
Bit 2
R/W
0
2
Mode Bit 2
R/W
0
ADDRESSES 0x14, 0x16, 0x44
0x11, 0x13, 0x15, 0x41, 0x43
1
Byte Count
Bit 1
R/W
0
1
Mode Bit 1
R/W
0
0
Byte Count
Bit 0
R/W
0
Page 40 of 59
0
Mode Bit 0
R/W
0
Figure
46.
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