CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet
CY7C66013-PVC
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CY7C66013-PVC Summary of contents
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... CY7C66011/12/13 CY7C66111/12/13 Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Cypress Semiconductor Corporation PRELIMINARY • 3901 North First Street • San Jose CY7C66011/12/13 CY7C66111/12/13 • CA 95134 • 408-943-2600 January 8, 1999 ...
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FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN CONFIGURATIONS ................................................................................................................. 8 4.0 PRODUCT SUMMARY TABLES .................................................................................................... 9 4.1 Pin Assignments ........................................................................................................................... 9 4.2 I/O Register Summary ................................................................................................................... 9 4.3 Instruction Set Summary ............................................................................................................ 11 5.0 PROGRAMMING MODEL ...
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Timer Interrupt ........................................................................................................................... 25 15.5 USB Endpoint Interrupts ........................................................................................................... 25 15.6 USB Hub Interrupt .....................................................................................................................25 15.7 DAC Interrupt ............................................................................................................................. 25 15.8 GPIO/HAPI Interrupt .................................................................................................................. Interrupt ................................................................................................................................26 16.0 USB OVERVIEW .........................................................................................................................26 16.1 USB Serial Interface ...
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Figure 10-1. Timer Register 0x24 (read only) .................................................................................. 20 Figure 10-2. Timer Register 0x25 (read only) .................................................................................. 20 Figure 10-3. Timer Block Diagram .................................................................................................... 21 2 Figure 11-1. HAPI/I C Configuration Register 0x09 (read/write) ................................................... 21 2 Figure 12-1. I ...
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... Internal memory — 256 bytes of RAM — EPROM (CY7C66011, CY7C66111) — EPROM (CY7C66012, CY7C66112) — EPROM (CY7C66013, CY7C66113) 2 • Integrated Master/Slave I C Controller (100 kHz) enabled through GPIO pins • Hardware Assisted Parallel Interface (HAPI) for data transfer to external devices • ...
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... The CY7C66011/12/13 and CY7C66111/12/13 are offered with three EPROM options. The CY7C66011 and CY7C66111 have EPROM. The CY7C66012 and CY7C66112 have EPROM. The CY7C66013 and CY7C66113 have EPROM. These parts include power-on reset logic, a watchdog timer, and a 12-bit free-running timer. The power-on reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000 ...
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Logic Block Diagram 6-MHz crystal PLL 48 MHz Clock 12-MHz Divider 8-bit CPU 12 MHz EPROM 4/6/8 KB RAM 256 byte 6 MHz 12-bit Timer Watch Dog Timer Power-On Reset PRELIMINARY USB Transceiver Repeater USB SIE Interrupt Controller P0[0] ...
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Pin Configurations CY7C66011/12/13 48-pin PDIP/SSOP/WC XTALOUT XTALIN V REF P1[3] P1[5] P1[7] P3[1] D+[0] D–[0] P3[3] GND D+[1] D–[1] P2[1] D+[2] D–[2] P2[3] P2[5] P2[7] GND P0[7] P0[5] P0[3] P0[1] PRELIMINARY TOP VIEW CY7C66111/12/13 56-pin SSOP ...
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Product Summary Tables 4.1 Pin Assignments Table 4-1. Pin Assignments Name I/O 48-Pin D+[0], D–[0] I/O 8,9 D+[1], D–[1] I/O 12,13 D+[2], D–[2] I/O 15,16 D+[3], D–[3] I/O 40,41 D+[4], D–[4] I/O 35,36 P0[7:0] I/O 21, 25, 22, 26, ...
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Table 4-2. I/O Register Summary (continued) Register Name I/O Address 2 HAPI and I C Configuration USB Device Address Counter Register EP A0 Mode Register EP A1 Counter Register EP A1 Mode Register EP A2 Counter Register ...
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Instruction Set Summary Table 4-3. Instruction Set Summary MNEMONIC operand HALT ADD A,expr data ADD A,[expr] direct ADD A,[X+expr] index ADC A,expr data ADC A,[expr] direct ADC A,[X+expr] index SUB A,expr data SUB A,[expr] direct SUB A,[X+expr] index SBB ...
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Programming Model 5.1 14-Bit Program Counter (PC) The 14-bit program counter (PC) allows access EPROM available with the CY7C66xxx architecture. The top 32 bytes of the ROM in the 8K part are reserved ...
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... Hub interrupt vector 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x0FFF 4 KB EPROM ends here (CY7C66011,CY7C66111 EPROM ends here (CY7C66012, CY7C66112) 0x17FF 0x1FDF 8 KB (-32) EPROM ends here (CY7C66013, CY7C66113) 13 CY7C66011/12/13 CY7C66111/12/13 ...
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Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-Bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on ...
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For USB applications, the firmware should set the DSP to the appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in the section on USB Device Endpoints ...
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The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect either an external oscillator or a crystal to these pins. A 6-MHz fundamental crystal can be connected to these pins to provide a reference frequency ...
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If the 1.024-ms timer interrupt service routine does not get executed for t occur. A Watch Dog Timer Reset lasts for 2 ms after which the microcontroller begins execution at ROM address 0x0000. The USB transmitter is disabled by a ...
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Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C66011/12/13 will always require that P3[7:5] be written with a ‘0.’ When the CY7C66111/12/13 ...
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P1[7] P1[6] P1[5] Figure 8-8. Port 1 Interrupt Enable 0x05 (read/write) P2[7] P2[6] P2[5] Figure 8-9. Port 2 Interrupt Enable 0x06 (read/write) not used P3[6] P3[5] Figure 8-10. Port 3 Interrupt Enable 0x07 (read/write) 9.0 DAC Port Internal Data Bus ...
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DAC[7] DAC[6] DAC[5] Figure 9-3. DAC Port Interrupt Enable 0x31 (write only additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register. Writing a ‘0’ bit selects negative ...
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11.0 HAPI and I C Configuration Register HAPI (Hardware Assisted Parallel Interface) provides for byte interface to an external device. I standard ...
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Table 11- Port Configuration Position Bit 12 Master Mode Controller 2 The I C interface consists of two registers, a control and status register, and a data register. ...
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Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. This bit is the only method for the firmware to determine that a slave receive transaction has been terminated ...
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The “USB Bus Reset Interrupt” (bit 5) will occur when a USB Bus Reset is received. The USB Bus Reset is a singled-ended zero (SE0) that lasts at least 12– SE0 is defined as the condition in which ...
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Table 15-1. Interrupt Vector Assignments Interrupt Vector Number Not Applicable 15.2 Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt latency = (Number of clock ...
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If one DAC pin has triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not ...
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USB Serial Interface Engine (SIE) The SIE allows the CY7C66xxx microcontroller to communicate with the USB host through the USB repeater portion of the hub. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that ...
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Then the hub repeater generates a “Hub Interrupt”, if the interrupt is enabled, to notify the microcontroller that there has been a change in the Hub downstream status. A high-speed (12 Mbps) USB device ...
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Table 17-1. Control Bit Definition for Downstream Ports Control Bits bit1 bit 0 Control Action 0 0 Not Forcing 0 1 Force Differential ‘1’ Force Differential ‘0’ Force SE0 state The data received on downstream ports ...
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The following table shows how the control bits are encoded for this register. Table 17-2. Control Bit Definition for Upstream Port Control Bits Control Action 000 Not Forcing (SIE Controls Driver) 001 Force D+[0] HIGH, D–[0] LOW 010 Force D+[0] ...
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Endpoint 0 Endpoint 0 Endpoint 0 SETUP IN Received Received Received Figure 18-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write) Bits[7:5] in the endpoint 0 mode registers (EPA0 and EPB0) are “sticky” status bits that are set ...
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Truth Tables Table 19-1. USB Register Mode Encoding Mode Encoding Setup Disable 0000 ignore Nak In/Out accept 0001 Status Out Only 0010 accept Stall In/Out 0011 accept Ignore In/Out 0100 accept Isochronous Out 0101 ignore Status In Only 0110 ...
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Table 19-2. Decode table for Table 19-3 : “Details of Modes for Differing Traffic Conditions” Properties of incoming packet Encoding End Point Mode Token count buffer Setup In Out The quality status of the DMA buffer ...
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Table 19-3. Details of Modes for Differing Traffic Conditions End Point Mode token count buffer Setup Packet (if accepting) See Table 19-1 Setup <= 10 data See Table 19-1 Setup > 10 junk See Table 19-1 ...
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Table 19-3. Details of Modes for Differing Traffic Conditions (continued) End Point Mode token count buffer Out > Out ...
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Electrical Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C, V Parameter General V Reference Voltage ref V Programming Voltage (disabled Supply Current—Suspend Mode SB1 I Input Leakage Current il USB Interface V Differential Input ...
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Switching Characteristics Parameter f Clock Rate OSC t Clock Period cyc t Clock HIGH time CH t Clock LOW time CL USB High Speed Signaling t Transition Rise Time r t Transition Fall Time f t Rise / Fall ...
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DATA out /CS & /OE STB DATA out OE /STB Data_Ready Data_Ready {Internal Write} {Internal Write} {Internal Addr} {Internal Addr} Figure 22-3. HAPI Read by External Interface from USB Microcontroller Table 22-1. HAPI Read Cycle Timing Parameters ...
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CS DATA /CS & /STB out STB DATA in OE /OE Latch_Empty Latch_Empty t STBLE {Internal Read} {Internal Read} {Internal Addr} {Internal Addr} Figure 22-4. HAPI Write by External Device to USB Microcontroller Table 22-2. HAPI Write Cycle Timing Parameters ...
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... Ordering Information EPROM Ordering Code Size CY7C66011-PVC 4 KB CY7C66011- CY7C66012-PVC 6 KB CY7C66012- CY7C66013-PVC 8 KB CY7C66013- CY7C66013-WVC 8 KB CY7C66111-PVC 4 KB CY7C66112-PVC 6 KB CY7C66113-PVC 8 KB Document #:38-00591-C 24.0 Package Diagrams PRELIMINARY Package Name Package Type O48 48-Pin (300-Mil) SSOP P25 48-Pin (600-Mil) PDIP ...
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Package Diagrams (continued) PRELIMINARY 48-Lead Shrunk Small Outline Package O48 56-Lead Shrunk Small Outline Package O56 41 CY7C66011/12/13 CY7C66111/12/13 51-85061-B 51-85062-B ...
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... Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...