CY7C66113C-PVXC Cypress Semiconductor Corp, CY7C66113C-PVXC Datasheet - Page 47

• Manufacturer Part Number: CY7C66113C-PVXC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-PVXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• No. Of I/o's: 31
• Eeprom Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Peripherals: DAC
• Rohs Compliant: Yes
• Controller Family/series: (8051) USB
• Embedded Interface Type: HAPI, I2C, USB
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1808

Table 17. Details of Modes for Differing Traffic Conditions (see
Register Summary
Document Number: 38-08024 Rev. *D
1
Isochronous endpoint (In)
0
0
Notes
5. B: Read and Write.
6. W: Write.
7. R: Read.
8. X: Unknown
1
1
1
0x06
0x07
0x15
0x00
0x01
0x02
0x03
0x04
0x05
0x08
0x09
0x10
0x11
0x12
0x13
0x14
0x16
0x1F
Addr
0 0
1 1
1 1
Port 0 Data
Port 1 Data
Port 2 Data
Port 3 Data
Port 0 Interrupt
Enable
Port 1 Interrupt
Enable
Port 2 Interrupt
Enable
Port 3 Interrupt
Enable
GPIO
Configuration
HAPI/I
Configuration
USB Device
Address A
EP A0 Counter
Register
EP A0 Mode
Register
EP A1 Counter
Register
EP A1 Mode
Register
EP A2 Counter
Register
EP A2 Mode
Register
USB Status and
Control
Register Name
In
Out
In
2
C
x
x
x
UC
UC
UC
P0.7
P1.7
P2.7
Reserved P3.6
P0.7 Intr
Enable
P1.7 Intr
Enable
P2.7 Intr
Enable
Reserved P3.6 Intr
Port 3
Config Bit
1
I
Position
Device
Address A
Enable
Data 0/1
Toggle
Endpoint0
SETUP
Received
Data 0/1
Toggle
STALL
Data 0/1
Toggle
STALL
Endpoint
Size
2
C
Bit 7
x
x
x
P0.6
P1.6
P2.6
CY7C66113C
only
P0.6 Intr
Enable
P1.6 Intr
Enable
P2.6 Intr
Enable
Enable
CY7C66113C
only
Port 3
Config Bit
0
Reserved LEMPTY
Device
Address
A Bit 6
Data
Valid
Endpoint0
IN
Received
Data Valid Byte
-
Data Valid Byte
-
Endpoint
Mode
Bit 6
UC
UC
UC
P0.5
P1.5
P2.5
P3.5
CY7C66113C
only
P0.5 Intr
Enable
P1.5 Intr
Enable
P2.5 Intr
Enable
P3.5 Intr
Enable
CY7C66113C
only
Port 2
Config Bit
1
Polarity
Device
Address
A Bit 5
Byte
Count
Bit 5
Endpoint0
OUT
Received
Count
Bit 5
-
Count
Bit 5
-
D+
Upstream
Bit 5
UC
UC
UC
P0.4
P1.4
P2.4
P0.4 Intr
Enable
P1.4 Intr
Enable
P2.4 Intr
Enable
ACK
Byte
Count
Bit 4
ACK
Byte
Count
Bit 4
P3.4
P3.4 Intr
Enable
Port 2
Config Bit
0
DRDY
Polarity
Device
Address
A Bit 4
Byte
Count
Bit 4
ACK
D–
Upstream
Bit 4
UC
UC
UC
Table 16
P0.3
P1.3
P2.3
P3.3
P0.3 Intr
Enable
P1.3 Intr
Enable
P2.3 Intr
Enable
P3.3 Intr
Enable
Port 1
Config Bit
1
Latch
Empty
Device
Address
A Bit 3
Byte
Count
Bit 3
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 bbbbbbbb
Byte
Count
Bit 3
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 bbbbbbbb
Byte
Count
Bit 3
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 bbbbbbbb
Bus
Activity
Bit 3
UC
UC
UC
for the decode legend) (continued)
P0.2
P1.2
P2.2
P3.2
P0.2 Intr
Enable
P1.2 Intr
Enable
P2.2 Intr
Enable
P3.2 Intr
Enable
Port 1
Config Bit
0
Data
Ready
Device
Address
A Bit 2
Byte
Count
Bit 2
Byte
Count
Bit 2
Byte
Count
Bit 2
Control
Bit 2
Bit 2
1
UC UC
1
CY7C66013C, CY7C66113C
UC
UC
P0.1
P1.1
P2.1
P3.1
P0.1 Intr
Enable
P1.1 Intr
Enable
P2.1 Intr
Enable
P3.1 Intr
Enable
Port 0
Config Bit
1
Port Width
bit 1
Device Ad-
dress
A Bit 1
Byte Count
Bit 1
Byte Count
Bit 1
Byte Count
Bit 1
Control
Bit 1
Bit 1
UC
UC
UC
P0.0
P1.0
P2.0
P3.0
P0.0 Intr
Enable
P1.0 Intr
Enable
P2.0 Intr
Enable
P3.0 Intr
Enable
Port 0
Config Bit
0
Port Width
bit 0
Device
Address
A Bit 0
Byte
Count
Bit 0
Byte
Count
Bit 0
Byte
Count
Bit 0
Control
Bit 0
No Change NAK
No Change ignore
No Change TX
Bit 0
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
wwwwwwww 00000000
wwwwwwww 00000000
wwwwwwww 00000000
wwwwwwww 00000000
bbbbbbbb
b-bbrrbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbrrbbbb
Read/Write/
Both
[5, 6, 7]
Page 47 of 59
11111111
11111111
11111111
-1111111
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
-0xx0000
Reset
Default/
yes
no
yes
[8]
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