CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 31

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

I
The I
compatible bus to signal the need for firmware interaction. This
generally involves reading the I
(Figure
reading the I
the Processor Status and Control Register
the subsequent transaction. The interrupt indicates that status
bits are stable and it is safe to read and write the I
When enabled, the I
interrupts on completion of the following conditions. The
referenced bits are in the I
■
■
■
■
■
■
The Continue/Busy bit is cleared by hardware prior to interrupt
conditions 1 to 4. When the Data Register is read or written,
firmware should configure the other control bits and set the
Continue/Busy bit for subsequent transactions. Following an
interrupt from master mode, firmware should perform only one
write to the Status and Control Register that sets the
Continue/Busy bit, without checking the value of the
Continue/Busy bit. The Busy bit may otherwise be active and I
register contents may be changed by the hardware during the
transaction, until the I
Document Number: 38-08024 Rev. *D
2
C Interrupt
In slave receive mode, after the slave receives a byte of data:
The Addr bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read or
write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next byte.
In slave receive mode, after a stop bit is detected: The
Received Stop bit is set, if the stop bit follows a slave receive
transaction where the ACK bit was cleared to 0, no stop bit
detection occurs.
In slave transmit mode, after the slave transmits a byte of data:
The ACK bit indicates if the master that requested the byte
acknowledged the byte. If more bytes are to be sent, firmware
writes the next byte into the Data Register and then sets the
Xmit MODE and Continue/Busy bits as required.
In master transmit mode, after the master sends a byte of
data. Firmware should load the Data Register if necessary, and
set the Xmit MODE, MSTR MODE, and Continue/Busy bits
appropriately. Clearing the MSTR MODE bit issues a stop
signal to the I
In master receive mode, after the master receives a byte of
data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing the
MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
leave the I
When the master loses arbitration: This condition clears the
MSTR MODE bit and sets the ARB Lost/Restart bit immediately
and then waits for a stop signal on the I
generate the interrupt.
2
C interrupt occurs after various events on the I
27) to determine the cause of the interrupt, loading and
2
2
C compatible hardware in the idle state.
C Data Register as appropriate, and finally writing
2
C compatible bus and return to the idle state.
2
2
C interrupt occurs.
C compatible state machines generate
2
C Status and Control Register.
2
C Status and Control Register
2
C compatible bus and
2
C compatible bus to
(Figure
2
28) to initiate
C registers.
2
2
C
C
USB Overview
The USB hardware includes a USB Hub repeater with one
upstream and four downstream ports. The USB Hub repeater
interfaces to the microcontroller through a full speed Serial
Interface Engine. An external series resistor of R
placed in series with all upstream and downstream USB outputs
to meet the USB driver requirements of the USB specification.
The CY7C66x13C microcontroller provides the functionality of a
compound device consisting of a USB hub and permanently
attached functions.
USB Serial Interface Engine
The
communicate with the USB host through the USB repeater
portion of the hub. The SIE simplifies the interface between the
microcontroller and USB by incorporating hardware that handles
the
microcontroller:
■
■
■
■
■
Firmware is required to handle the following USB interface tasks:
■
■
■
■
USB Enumeration
The internal hub and any compound device function are
enumerated under firmware control. The hub is enumerated first,
followed by any integrated compound function. After the hub is
enumerated, the USB host reads hub connection status to
determine which (if any) of the downstream ports need to be
enumerated. The following is a brief summary of the typical
enumeration process of the CY7C66x13C by the USB host. For
a detailed description of the enumeration process, refer to the
USB specification.
In this description, “Firmware” refers to embedded firmware in
the CY7C66x13C controller.
1. The host computer sends a SETUP packet followed by a
2. Firmware decodes the request and retrieves its Device
3. The host computer performs a control read sequence and
4. After receiving the descriptor, the host sends a SETUP packet
Bit stuffing and unstuffing
Checksum generation and checking
ACK/NAK/STALL
Token type identification
Address checking.
Coordinate enumeration by responding to SETUP packets
Fill and empty the FIFOs
Suspend and Resume coordination
Verify and select DATA toggle values.
DATA packet to USB address 0 requesting the Device
descriptor.
descriptor from the program memory tables.
Firmware responds by sending the Device descriptor over the
USB bus, via the on-chip FIFOs.
followed by a DATA packet to address 0 assigning a new USB
address to the device.
following
SIE
allows
USB
CY7C66013C, CY7C66113C
the
bus
CY7C66x13C
activity
independently
microcontroller
Page 31 of 59
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must be
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