CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 44

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

stage OUT token. The firmware needs to update the mode for
the SIE to respond appropriately. See
on what modes are changed by the SIE. A disabled endpoint
remains disabled until changed by firmware, and all endpoints
reset to the disabled mode (0000). Firmware normally enables
the endpoint mode after a SetConfiguration request.
Any SETUP packet to an enabled endpoint with mode set to
accept SETUPs are changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP sends an ACK
handshake to a valid SETUP token.
The response of the SIE are summarized as follows:
■
■
■
■
■
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Document Number: 38-08024 Rev. *D
Table 16. Decode Table for
3
Endpoint Mode
encoding
Legend:
The SIE only responds to valid transactions, and ignores invalid
ones.
The SIE generates an interrupt when a valid transaction is
completed or when the FIFO is corrupted. FIFO corruption
occurs during an OUT or SETUP transaction to a valid internal
address, that ends with a invalid CRC.
An incoming Data packet is valid if the count is < Endpoint Size
+ 2 (includes CRC) and passes all error checking.
An IN is ignored by an OUT configured endpoint and visa versa.
The IN and OUT PID status is updated at the end of a
transaction.
The SETUP PID status is updated at the beginning of the Data
packet phase.
2
1
0
Received Token
(SETUP/IN/OUT)
Token
TX: transmit
RX: receive
x: don’t care
Properties of
Incoming Packets
count
The number of received bytes
available for Control endpoint only
Table 17
buffer
The quality status of the DMA buffer
UC : unchanged
TX0:Transmit 0 length packet
Table 12
dval
The validity of the received data
Changes to the Internal Register made by the SIE on receiving an incoming
packet from the host
for more details
DTOG
Data0/1 (bit7 Figure 17-4)
Data Valid (bit 6, Figure 17-4)
DVAL
Byte Count (bits 0..5, Figure 17-4)
COUNT
The control endpoint has three status bits for identifying the
token type received (SETUP, IN, or OUT), but the endpoint must
be placed in the correct mode to function as such. Non control
endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an
ending ACK, are changed by the SIE to a corresponding mode
which NAKs subsequent packets following the ACK. Exceptions
are modes 1010 and 1110.
■
The entire Endpoint 0 mode register and the Count register are
locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are
only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete.
This represents about a 1 μs window in which the CPU is locked
from register writes to these USB registers. Normally the
firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information.
The interlock on the Mode and Count registers ensures that
the firmware recognizes the changes that the SIE might have
made during the previous transaction. Note that the setup bit
of the mode register is NOT locked. This means that before
writing to the mode register, firmware must first read the register
to make sure that the setup bit is not set (which indicates a
setup was received, while processing the current USB request).
This read unlocks the register. So care must be taken not to
overwrite the register elsewhere.
PID Status Bits
(Bit[7..5], Figure 17-2)
Setup
In
CY7C66013C, CY7C66113C
Out
ACK
Acknowledge phase completed
3
Endpoint Mode bits
Changed by the SIE
2 1 0 Response
SIE’s Response
to the Host
Page 44 of 59
Interrupt
Int
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