CY7C68013A-56PVXI Cypress Semiconductor Corp, CY7C68013A-56PVXI Datasheet - Page 43
![IC MCU USB PERIPH HI SPD 56-SSOP](/photos/6/50/65056/428-56-ssop_sml.jpg)
CY7C68013A-56PVXI
Manufacturer Part Number
CY7C68013A-56PVXI
Description
IC MCU USB PERIPH HI SPD 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXI
Program Memory Type
ROMless
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
- 40 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1944-5
CY7C68013A-56PVXI
CY7C68013A-56PVXI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56PVXI
Manufacturer:
CY
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5 530
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Manufacturer:
CY
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Company:
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CY7C68013A-56PVXI
Manufacturer:
Cypress Semiconductor
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135
Part Number:
CY7C68013A-56PVXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
10.7 Slave FIFO Synchronous Read
Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
Parameter
Parameter
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
FLAGS
SLOE
SLRD
DATA
IFCLK
Figure 18. Slave FIFO Synchronous Read Timing Diagram
Description
Description
t
OEon
N
t
SRD
t
IFCLK
t
RDH
t
XFLG
t
XFD
N+1
20.83
20.83
18.7
12.7
Min
Min
3.7
0
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
t
OEoff
[21]
[21]
[20]
Max
10.5
10.5
Max
10.5
10.5
13.5
200
9.5
15
11
Page 43 of 62
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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