CY7C68013A-56PVXI Cypress Semiconductor Corp, CY7C68013A-56PVXI Datasheet - Page 6
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CY7C68013A-56PVXI
Manufacturer Part Number
CY7C68013A-56PVXI
Description
IC MCU USB PERIPH HI SPD 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXI
Program Memory Type
ROMless
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
- 40 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1944-5
CY7C68013A-56PVXI
CY7C68013A-56PVXI
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Manufacturer
Quantity
Price
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Table 4. Individual FIFO/GPIF Interrupt Sources
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter to its stack then jumps to address
0x0053, where it expects to find a “jump” instruction to the ISR
Interrupt service routine.
3.9 Reset and Wakeup
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA the reset period must enable stabilization of
the crystal and the PLL. This reset period must be approximately
Document #: 38-08032 Rev. *M
Note
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.
Priority
10
11
12
13
14
1
2
3
4
5
6
7
8
9
INT4VEC Value
AC
8C
9C
80
88
90
94
98
A0
A4
A8
B0
B4
84
GPIFDONE
GPIFWF
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
5 ms after VCC reaches 3.0V. If the crystal input pin is driven by
a clock signal the internal PLL stabilizes in 200 μs after VCC has
reached 3.0V.
Figure 2
applied during operation. A power on reset is defined as the time
reset that is asserted while power is being applied to the circuit.
A powered reset is when the FX2LP powered on and operating
and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation. For more infor-
mation about reset implementation for the FX2 family of products
visit http://www.cypress.com.
on page 7 shows a power on reset condition and a reset
[3]
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Notes
Page 6 of 62
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