CY7C63743-PC Cypress Semiconductor Corp, CY7C63743-PC Datasheet - Page 29

• Manufacturer Part Number: CY7C63743-PC
• Description: IC MCU 8K LS USB/PS-2 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1324

21.3
The following sections provide details on the different types of
interrupt sources.
Bit 7: Wake-up Interrupt Enable
Bit 6: GPIO Interrupt Enable
Bit [5:4]: Capture Timer A and B Interrupts
There are two capture timer interrupts, one for each
associated pin. Each of these interrupts occurs on an enabled
Document #: 38-08022 Rev. *B
Read/Write
Bit Name
The internal wake-up timer is normally used to wake the
part from suspend mode, but it can also provide an interrupt
when the part is awake. The wake-up timer is cleared
whenever the Wake-up Interrupt Enable bit is written to a 0,
and runs whenever that bit is written to a 1. When the inter-
rupt is enabled, the wake-up timer provides periodic inter-
rupts at multiples of period, as described in Section 11.2.
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Each GPIO pin can serve as an interrupt input. During a
reset, GPIO interrupts are disabled by clearing all GPIO
interrupt enable registers. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding
input pin. These registers are shown in Figure 21-4 for Port
0 and Figure 21-5 for Port 1. In addition to enabling the
desired individual pins for interrupt, the main GPIO interrupt
must be enabled, as explained in Section 21.0.
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers. Setting a Polarity bit to ‘0’ allows an interrupt on
a falling GPIO edge, while setting a Polarity bit to ‘1’ allows
an interrupt on a rising GPIO edge. The Polarity Registers
reset to 0 and are shown in Figure 21-6 for Port 0 and
Figure 21-7 for Port 1.
All of the GPIO pins share a single interrupt vector, which
means the firmware will need to read the GPIO ports with
enabled interrupts to determine which pin or pins caused
an interrupt.The GPIO interrupt structure is illustrated in
Figure 21-8.
Note that if one port pin triggered an interrupt, no other port
pins can cause a GPIO interrupt until that port pin has re-
turned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The CY7C637xx does
not assign interrupt priority to different port pins and the
Port Interrupt Enable Registers are not affected by the in-
terrupt acknowledge process.
1 = Enable
0 = Disable
Reset
Bit #
Interrupt Sources
Wake-up
Interrupt
Enable
R/W
7
0
Interrupt
Figure 21-1. Global Interrupt Enable Register (Address 0x20)
Enable
GPIO
R/W
6
0
FOR
FOR
Intr. Enable
Capture
Timer B
R/W
5
0
Intr. Enable
Capture
Timer A
R/W
4
0
edge of the selected GPIO pin(s). For each pin, rising and/or
falling edge capture interrupts can be in selected. Refer to
Section 19.0. These interrupts are independent of the GPIO
interrupt, described in the next section.
Bit 3: SPI Interrupt Enable
The SPI interrupt occurs at the end of each SPI byte trans-
action, at the final clock edge, as shown in Figure 17-4. After
the interrupt, the received data byte can be read from the SPI
Data Register, and the TCMP control bit will be high
Bit 2: 1.024-ms Interrupt Enable
Bit 1: 128-µs Interrupt Enable
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
The 1.024-ms interrupts are periodic timer interrupts from
the free-running timer (based on the 6-MHz clock). The
user should disable this interrupt before going into the sus-
pend mode to avoid possible conflicts between servicing
the timer interrupts (128-µs interrupt and 1.024-ms inter-
rupt) first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 1.024 ms.
0 = Disable.
The 128-µs interrupt is another source of timer interrupt
from the free-running timer. The user should disable both
timer interrupts (128-µs and 1.024-ms) before going into
the suspend mode to avoid possible conflicts between ser-
vicing the timer interrupts first or the suspend request first
when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 128 µs.
0 = Disable.
The function of this interrupt is selectable between detec-
tion of either a USB bus reset condition, or PS/2 activity.
The selection is made with the USB-PS/2 Interrupt Mode
bit in the USB Status and Control Register (Figure 13-1). In
either case, the interrupt will occur if the selected condition
exists for 256 µs, and may occur as early as 128 µs.
Interrupt
Enable
R/W
SPI
3
0
1.024-ms
Interrupt
Enable
R/W
2
0
Interrupt
128-µs
Enable
R/W
1
0
CY7C63722
CY7C63723
CY7C63743
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PS/2 Activity
Intr. Enable
USB Bus
Reset /
R/W
0
0