CY7C63743-PC Cypress Semiconductor Corp, CY7C63743-PC Datasheet - Page 32

IC MCU 8K LS USB/PS-2 24-DIP

CY7C63743-PC

Manufacturer Part Number
CY7C63743-PC
Description
IC MCU 8K LS USB/PS-2 24-DIP
Manufacturer
Cypress Semiconductor Corp
Series
enCoRe™r
Datasheets

Specifications of CY7C63743-PC

Applications
USB Microcontroller
Core Processor
M8B
Program Memory Type
OTP (8 kB)
Controller Series
CY7C637xx
Ram Size
256 x 8
Interface
PS2, USB
Number Of I /o
16
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1324

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C63743-PC
Manufacturer:
CYPRESS
Quantity:
2 094
Part Number:
CY7C63743-PC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Bit [7:0]: P1[7:0] Interrupt Polarity
22.0
The following tables give details on mode setting for the USB
Serial Interface Engine (SIE) for both the control endpoint
(EP0) and non-control endpoints (EP1 and EP2).
Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints
Note:
Document #: 38-08022 Rev. *B
3.
Disable
NAK IN/OUT
Status OUT Only
STALL IN/OUT
Ignore IN/OUT
Reserved
Status IN Only
Reserved
NAK OUT
ACK OUT(
ACK OUT
NAK OUT - Status IN
ACK OUT - NAK IN
NAK IN
ACK IN
ACK IN(
NAK IN - Status OUT
ACK IN - Status OUT
GPIO
Pin
1 = Rising GPIO edge
0 = Falling GPIO edge
IRA
STALL bit is the bit 7 of the USB Non-Control Device Endpoint Mode registers. Refer to Section 14.3 for more explanation.
1 = Enable
0 = Disable
Mode
(STALL
STALL
USB Mode Tables
(STALL
STALL
[3]
[3]
=0)
=1)
[3]
[3]
=1)
=0)
Port Bit Interrupt
Enable Register
Encoding
0000
0001
0010
0011
0100
0101
0110
1000
1001
1001
1010
1011
1100
1101
1101
0111
1110
1111
Port Bit Interrupt
Polarity Register
M
U
X
SETUP
Accept
Accept
Accept
Accept
Accept
Accept
Accept
Accept
Accept
FOR
FOR
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Figure 21-8. GPIO Interrupt Diagram
TX 0 Byte
TX Count
TX 0 Byte
TX Count
TX Count
STALL
STALL
STALL
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
1 = Enable
0 = Disable
NAK
NAK
NAK
NAK
IN
(1 input per
OR Gate
GPIO pin)
Always
STALL
STALL
STALL
Ignore
Check
Ignore
Ignore
Ignore
Ignore
Ignore
Check
Check
OUT
NAK
NAK
ACK
NAK
ACK
(Bit 6, Register 0x20)
GPIO Interrupt
Global
Enable
Comments
Ignore all USB traffic to this endpoint
On Control endpoint, after successfully sending an ACK
handshake to a SETUP packet, the SIE forces the
endpoint mode (from modes other than 0000) to 0001.
The mode is also changed by the SIE to 0001 from mode
1011 on issuance of ACK handshake to an OUT.
For Control endpoints
For Control endpoints
For Control endpoints
Reserved
For Control Endpoints
Reserved
In mode 1001, after sending an ACK handshake to an
OUT, the SIE changes the mode to 1000
This mode is changed by the SIE to mode 1000 on
issuance of ACK handshake to an OUT
This mode is changed by the SIE to mode 0001 on
issuance of ACK handshake to an OUT
An ACK from mode 1101 changes the mode to 1100
This mode is changed by the SIE to mode 1100 on
issuance of ACK handshake to an IN
An ACK from mode 1111 changes the mode to 1110
This mode is changed by the SIE to mode 1110 on
issuance of ACK handshake to an IN
1
GPIO Interrupt
Flip Flop
D
CLR
Q
Interrupt
Encoder
Priority
CY7C63722
CY7C63723
CY7C63743
Page 32 of 49
Interrupt
IRQout
Vector

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